IEEE Journal of Solid-State Circuits

Article	Citations
Information For Authors	110
IEEE JOURNAL OF SOLID-STATE CIRCUITS	89
Table of Contents	86
Table of Contents	79
Table of Contents	77
Table of Contents	76
Introducing IEEE Collabratec	68
IEEE Journal of Solid-State Circuits Publication Information	68
Together, we are advancing technology	61
Table of Contents	61
Together, we are advancing technology	61
Information For Authors	60
Introducing IEEE Collabratec	59
Introducing IEEE Collabratec	58
Table of Contents	58
IEEE Journal of Solid-State Circuits Publication Information	58
TechRxiv: Share Your Preprint Research with the World!	58
An Emulated Curve Assisted Fast-Transient Buck Converter With One-Cycle Charge Balance	55
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier	55
Guest Editorial 2024 Custom Integrated Circuits Conference	55
Introducing IEEE Collabratec	53
TechRxiv: Share Your Preprint Research with the World!	53
Introducing IEEE Collabratec	52
A 140 dB-DR Light-to-Digital Converter Using Current-Domain Hybrid Zoom for Baseline Cancellation and Interference Compensation	50
A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference	50

MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection	49
A 26/28/39-GHz Reconfigurable Phased-Array Receiver Front-End With Built-In Calibration Technique for 5G New Radio	48
A Sub-Nanosecond Pulsed VCSEL Driver With PVT-Compensated Constant Current, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety	48
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators	48
Modular DR- and CMR-Boosted Artifact-Resilient EEG Headset With Distributed Pulse-Based Feature Extraction and Neuro-Inspired Boosted-SVM Classifier	48
A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping	47
A 0.65-mW-to-1-W Photovoltaic Energy Harvester With Irradiance-Aware Auto-Configurable Hybrid MPPT Achieving >95% MPPT Efficiency and 2.9-ms FOCV Transient Time	47
Guest Editorial 2022 Custom Integrated Circuits Conference	46
Information For Authors	46
Table of Contents	46
A 49.8-mm2 IR-UWB Transmitter With Co-Designed Power Amplifier and Antenna for Neural Implants With Extended Transmission Range	45
NeuroFlare: An mm3-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	44
Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET	43
A Polar Phase-Tracking Receiver With Two-Point Injection Technique	43
An E-Band FMCW Radar Receiver With Arbitrary-Path Spillover Cancellation	43
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance	43
Table of Contents	42
New Associate Editor	42
Table of Contents	42
TechRxiv: Share Your Preprint Research with the World!	42
Information For Authors	42
Introducing IEEE Collabratec	42
Information For Authors	42
BioCas 2022	41
Table of Contents	41
Table of Contents	40
IEEE Access	40
Together, we are advancing technology	39
Table of Contents	39
Together, we are advancing technology	38
Table of contents	38
IEEE JOURNAL OF SOLID-STATE CIRCUITS	38
New Associate Editor	38
Table of Contents	37
Introducing IEEE Collabratec	37
IEEE JOURNAL OF SOLID-STATE CIRCUITS	37
TechRxiv: Share Your Preprint Research with the World!	37
TechRxiv: Share Your Preprint Research with the World!	36
Message From the Incoming Editor-in-Chief	36
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	36
IEEE JOURNAL OF SOLID-STATE CIRCUITS	35
IEEE JOURNAL OF SOLID-STATE CIRCUITS	35
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems	35
Table of Contents	35
A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios	35
Table of Contents	35
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications	34
A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter	34
A 2.5–5-V Input 100-V Output 86.2% Peak Efficiency Fibonacci–Dickson Hybrid Converter for Acoustic Surface Audio Driver	33
A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System	33

A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	33
Information For Authors	33
IEEE Journal of Solid-State Circuits Publication Information	33
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology	33
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory	33
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning	33
Table of Contents	33
A 334 μW 0.158 mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom–Cook Multiplication	32
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit	32
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging	32
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	32
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces	32
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization	32
Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays	32
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining	32
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique	32
A 1 mm ×1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0–40-mM/L Detection Range With ΔΣ Backscatter Technique	32
A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier	31
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond	31
A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os	31
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs	31
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications	31
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface	31
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge	30
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator	30
A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS	30
A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors	30
Voltage Level Detection for Near-V TH Computing	29
A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed VCF Calibration and Smooth Mode Transition	29
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link	29
A Thin Elastic NFC Forum Type 1 Compatible RFID Tag	29
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter	29
A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk CMOS	29
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers	29
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL	29
A Low-Stimulus-Scattering Pixel-Sharing Sub-Retinal Prosthesis SoC With Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling	29
A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers	29
A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range	28
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch	28
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing	28
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering	28
A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of Living Cells	28
0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation	27
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm Psat and 26.5% PAE in 16-nm FinFET CMOS	27
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone	27
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)	27
A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications	26
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel	26
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization	26
Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference	26
A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers	26
A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control	26
An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS	26
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver	26
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	26
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	26
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC–DC Converters	26
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN	26
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion	25
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth	25
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique	25
A 52–73-GHz LNA With Tri-Coupled Transformer for G m Boosting and Enhanced Noise Canceling	25
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	25
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation	25
A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection	25
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology	25
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)	25
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method	25
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS	24
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode	24
A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost Converter With Duty-Dependent Charge Topology for 1.2-A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Ap	24
A 3.36-μm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle Clocked Recharging Technique With an Intermediate Most-Significant-Bit Readout	24
Erratum to “High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure”	24
A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering	24
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	24
New Associate Editor	24
A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC–DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity	24
A 0.45-THz 2-D Scalable Radiator Array With 28.2-dBm EIRP Using an Elliptical Teflon Lens	24
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance	23
A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR	23

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer	23
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	23
A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants	23
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations	23
A 48–80-V Input 2-MHz Adaptive ZVT-Assisted Bus Converter With Light-Load Efficiency Improvement	23
Magnetoelectric Bio-Implants Powered and Programmed by a Single Transmitter for Coordinated Multisite Stimulation	23
A −121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter Nonlinearity Suppression	23
A Wireless Somatosensory Feedback System Using Human Body Communication	23
A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping	22
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS	22
A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From −45 °C to 85 °C	22
A mm-Wave Switched-Capacitor RFDAC	22
A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit	22
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS	22
Physical Layer Security Through Directional Modulation With Spatio-Temporal Millimeter-Wave Transmitter Arrays	22
HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs	22
Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions	22
EQZ-LDO: A Secure Digital Low Dropout Regulator Armed With Detection-Driven Protection Against Correlation Power Analysis	22
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	22
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	21
An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation	21
A Miniaturized Wireless Neural Implant With Body-Coupled Power Delivery and Data Transmission	21
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters	21
A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS	21
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS	21
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference	21
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ∘C (3σ) Inaccuracy From -55 ∘C to 125 ∘C	21
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces	21
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range	21
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC)	21
A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology	21
A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier	21
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor	21
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm	21
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	21
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop	21
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	21
A Double Pulse Overlapping Laser Diode Driver With Minimum 100-ps Pulse for LiDAR System	21
Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs	21
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications	21
A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band	21
eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations	21
Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging	21
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	21
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	20
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication	20
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time	20
An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural Sensing Interfaces	20
A High-Efficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 5G NR Power Amplifier	20
Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control	20
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	20
A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS	20
A 1.76 mW, 355-fps, Electrical Impedance Tomography System With a Simple Time-to-Digital Impedance Readout for Fast Neonatal Lung Imaging	20
A β-Compensated NPN-Based Temperature Sensor With ±0.1 °C (3σ) Inaccuracy From -55 °C to 125 °C and 200fJ · K² Resolution FoM	20
A 94.4% Peak Efficiency Coupled-Inductor Hybrid Step-Up Converter With Load-Independent Output Voltage Ripple	20
Table of Contents	19
A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS	19
A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes	19
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)	19
An Integrated-Circuit Node for High-Spatiotemporal Resolution Time-Domain Near-Infrared Diffuse Optical Tomography Imaging Arrays	19
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS	19
A Sub-400-nW Real-Time Event-Driven Spectrogram Extraction Unit in 28-nm FD-SOI CMOS for Keyword Spotting Application	19
A Series-Parallel Switched-Photovoltaic DC–DC Converter	19
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains	19
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	19
A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication	19
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration	19
A Reconfigurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver Localization for Low-Latency Joint Communication and Sensing	19
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC	19
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss	19
A 28-GHz Four-Channel Beamforming Front-End IC With Dual-Vector Variable Gain Phase Shifters for 64-Element Phased Array Antenna Module	19
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer	19
Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification	19
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ	19
A Time-Domain Current-Mode Buck Converter With a PI Compensator Incorporating an Infinite Phase Shift Delay Line	18
An RF MEMS Sensor Driver/Readout SoC With Resonant Frequency Shift and Closed-Loop Envelope Regulation for Portable Microplastic Detection	18
A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC	18
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling	18
OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC	18
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge	18
Flip-Chip Aperture Coupled D-Band Active Radiator Tiles in 22-nm CMOS FDSOI	18
Table of Contents	18
VISTA: A Memory-Efficient CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration	18
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports	18
Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS	18
A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC	18
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-$\mu$s Retention Time	18
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer	18
An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques	18
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	18
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness	17
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI	17
A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range	17
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation	17
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking	17