OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Journal of Solid-State Circuits is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	118
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	93
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	92
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	90
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	87
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	82
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ^∘C (3σ) Inaccuracy From -55 ^∘C to 125 ^∘C	73
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	70
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	69
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	65
Table of Contents	65
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	65
IEEE JOURNAL OF SOLID-STATE CIRCUITS	64
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier	63
Message From the Incoming Editor-in-Chief	63
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer	62
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators	61
Table of Contents	59
IEEE JOURNAL OF SOLID-STATE CIRCUITS	58
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	58
NeuroFlare: An mm³-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	58
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	57
Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur	55
Table of Contents	55
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver	54

A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI	52
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS	52
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead	50
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology	50
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	49
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode	49
A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling	49
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication	48
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC–DC Converters	46
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P _sat for 5G NR FR2 Operation	46
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel	45
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion	45
A mm-Wave Switched-Capacitor RFDAC	44
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting	44
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode	44
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory	44
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	44
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	43
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time	43
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports	42
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS	42
Information For Authors	41
RFIC 2023 Call for Papers	41
Table of Contents	41
Table of Contents	40
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET	40
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC	40
IEEE JOURNAL OF SOLID-STATE CIRCUITS	40
TechRxiv: Share Your Preprint Research With the World!	39
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level	39
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs	39
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing	39
Table of Contents	38
An 85-GHz Power Amplifier Utilizing a Transformer-Based Power Combiner Operating Beyond the Self-Resonance Frequency	38
A Bidirectional USB Power Delivery Voltage-Regulating Cable	38
A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout	38
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers	38
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers	38
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip	37
TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration	37
New Associate Editor	37
Erratum to “A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain” [Nov 21 3360-3374]	37
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium	37
A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics	37
On-Chip Condition-Adaptive Δ f ³ EMI Control for Switching Power ICs	36
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation	35
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors	35
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation	35
New Associate Editor	35
A Fully Integrated 4:1 DC–DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators	35

A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing	35
A 22-nm Delta–Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing	35
A Single Li-Ion Battery Powered Buck Converter With >90% Efficiency Over 10-μA to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology	35
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET	33
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference	33
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS	33
A Fully Energy-Autonomous Temperature-to-Time Converter Powered by a Triboelectric Energy Harvester for Biomedical Applications	33
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS	33
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application	33
Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode	33
Analysis and Design of a 10.4-ENOB 0.92–5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications	33
Table of Contents	33
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology	32
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM	32
A 1920 × 1080 Array 2-D/3-D Image Sensor With 3-μ s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel	32
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications	31
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing	31
A 6-GHz Continuous-Time Bandpass TEXPRESERVE0 ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver	31
Table of Contents	31
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications	31
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS	31
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS	30
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture	30
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement	30
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique	30
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces	30
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology	30
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC	30
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS	30
Table of Contents	30
A Full-Duplex Rake Receiver Using RF Code-Domain Signal Processing for Multipath Environments	30
A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD	29
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier	29
New Associate Editor	29
A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking	29
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction	29
Introducing IEEE Collabratec	29
A 2.5–20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery	29
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS	28
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation	28
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme	28
New Associate Editor	28
A 56-GHz Fractional-N PLL With 110-fs Jitter	28
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging	28
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS	28
A 0.8-V BJT-Based Temperature Sensor With an Inaccuracy of ±0.4 °C (3σ) From −40 °C to 125 °C in 22-nm CMOS	27
A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail	27
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips	27
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications	27
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS	27
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity	27
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation	27
TechRxiv: Share Your Preprint Research With the World!	27
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS	27
Design and Characterization of a 10-MHz GaN Gate Driver Using On-Chip Feed-Forward Gaussian Switching Regulation for EMI Reduction	27
A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC	27
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing	26
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing	26
A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz	26
A 0.35-V 5,200-μm² 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator	26
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer	26
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing	26
An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation	26
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging	26
Optically Synchronized Phased Arrays in CMOS	26
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications	26
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features	26
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm³ Field of View	26
2021 Index IEEE Journal of Solid-State Circuits Vol. 56	26
An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With −93-dB THD+N, 113-dB SNR, and 93% Efficiency	26
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End	25
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range	25
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive	25
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	25
A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 °C to 165 °C Consuming 210 μW at 70 MHz	25
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium	25
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification	25
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer	25
TechRxiv: Share Your Preprint Research with the World!	25
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback	25

Erratum to “A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System-on-Chip”	25
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction	25
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL	24
Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning	24
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques	24
New Associate Editor	24
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit	24
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS	24
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI	24
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation	24
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS	24
A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration	23
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques	23
A 420-GHz Sub-5-μm Range Resolution TX–RX Phase Imaging System in 40-nm CMOS Technology	23
A 0.00175 mm² and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm	23
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL	23
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement	23
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology	23
A Self-Calibrated Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor	23
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mmTEXPRESERVE0 Density in 28nm CMOS	23
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking	23
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient	23
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection	23
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC	22
A 4.9–7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application	22
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage	22
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving $-$28.5-dBm Sensitivity	22
A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping	22
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation	22
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification	22
Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications	22
A Recursive N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting	22
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces	22
A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation	22
A 3.1-μW Analog-Assisted Zoom Histogramming TDC in 35-μm Pixel Pitch for Flash LiDAR Sensor	21
New Associate Editor	21
TechRxiv: Share Your Preprint Research With the World!	21
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security	21
IEEE JOURNAL OF SOLID-STATE CIRCUITS	21
TechRxiv: Share Your Preprint Research With the World!	21
Table of Contents	21
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm	21
TechRxiv: Share Your Preprint Research with the World!	21
Table of Contents	21
Table of Contents	21
A 28-GHz, Multi-Beam, Decentralized Relay Array	20
A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter	20
An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation	20
IEEE Journal of Solid-State Circuits Information for Authors	20
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond	20
New Associate Editor	20
TechRxiv: Share Your Preprint Research with the World!	20
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset	20
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy	20
New Associate Editor	20
A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection Crystal Oscillator	20
A 2.46-mm² Miniaturized Brain-Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding	20
Erratum to “A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver”	20
IEEE JOURNAL OF SOLID-STATE CIRCUITS	20
Introducing IEEE Collabratec	20
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines	20
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets	20
A 200-GHz Power Amplifier With 18.7-dBm P _sat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification	20
IEEE Journal of Solid-State Circuits Publication Information	20
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL	20
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting	20
Table of Contents	20
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium	20
A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector	19
Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56fmax: An Analytical Approach on Reversed Feedback Amplifiers	19
A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction	19
Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”	19
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays	19
A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically-Switching Passive Body Channel Communication	19
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations	19
A 0.033-mm² 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF	19
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration	19
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips	19
A Six-Phase Harmonic-Rejection Digital Transmitter	19
A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration	19
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR	19
A 2.2-ps Time-of-Flight Resolution Frequency-Domain fNIRS Readout IC With a Dynamic Architecture and Cross-Coupling-Free Intensity and Phase-to-Digital Converter	19
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling	19
A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration	19
A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current	18
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM	18
A 48–56 GHz >1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna	18
A 20-Gb/s/Line Single-Ended Transceiver With Coupling-Balanced Crosstalk-Cancellation for Shield-Less 1.5-μm-Pitch Interconnect	18
IEEE Journal of Solid-State Circuits	18
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference	18
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning and Online Tuning	18
Information For Authors	18
New Associate Editor	18
NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core	18
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack Depth Sensing	18