OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Journal of Solid-State Circuits is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)

Article	Citations
Message From the Incoming Editor-in-Chief	116
IEEE JOURNAL OF SOLID-STATE CIRCUITS	108
Table of Contents	106
Table of Contents	94
IEEE JOURNAL OF SOLID-STATE CIRCUITS	93
A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication	92
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device	91
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication	90
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	87
A 60-V High-Side / In-Line Instrumentation Amplifier With 54-V/ μ s CM Transient Tolerance and 115-dB Dynamic Range	74
NeuroFlare: An mm³-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	70
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	69
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC–DC Converters	69
Table of Contents	66
A Time-Domain Accuracy-Boosted Temperature Compensated Crystal Oscillator	66
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS	65
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	65
Table of Contents	64
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators	63
A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues	63
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	62
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	60
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time	60
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI	58
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	57

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology	57
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	56
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	55
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier	55
Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK	54
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	54
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	53
A 3-nm FinFET 563-kbit 35.5-Mbit/mm ² Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode	53
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer	52
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead	51
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	51
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	50
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	50
A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling	50
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver	49
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ^∘C (3σ) Inaccuracy From -55 ^∘C to 125 ^∘C	48
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	48
A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference	48
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P _sat for 5G NR FR2 Operation	47
TechRxiv: Share Your Preprint Research With the World!	46
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	46
RFIC 2023 Call for Papers	46
Table of Contents	46
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS	46
Table of Contents	45
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET	44
A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing	44
Information For Authors	43
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing	43
A K / Ka -Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS	43
A Continuous-Time Zoom ADC With Coarse Noise-Shaping ADC and Interstage Low-Pass Filter	43
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation	43
A Single Li-Ion Battery Powered Buck Converter With >90% Efficiency Over 10-μA to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology	43
A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD	42
A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout	41
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC	41
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference	40
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation	40
IEEE Journal of Solid-State Circuits Publication Information	39
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip	39
New Associate Editor	39
New Associate Editor	39
Table of Contents	39
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium	39
Erratum to “A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration”	38
A +43.3-dBm IIP ₃ , Low-Power Transimpedance Amplifier Employing a Switched-Capacitor Amplifier-Based Transition-Band Pole-Zero Doublets Compensation	38
A Fully Integrated 4:1 DC–DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators	38
A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution	38
A LiDAR–PNN Pipelined Processor With Cylindrical Bin Partitioning and Halo Indexing for 3-D Perception in Outdoor Autonomous Driving Applications	38
A Bidirectional USB Power Delivery Voltage-Regulating Cable	38

A Filter-Embedded Pipe-SAR ADC With Progressive Conversion and Floating Charge Transfer Amplifier	38
Analysis and Design of a 10.4-ENOB 0.92–5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications	37
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level	37
A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing	37
A Dual-Path Topology for Single-Inductor Dual-Output DC–DC Converters	37
On-Chip Condition-Adaptive Δ f ³ EMI Control for Switching Power ICs	37
Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode	36
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS	36
A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics	36
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM	36
TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration	35
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers	35
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET	35
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers	35
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology	35
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application	34
Dual-Mode Inverter-Based Write Termination Scheme for Energy- and Area-Efficient Write Operation in 28-nm 1T1MTJ STT-MRAM	34
Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure	34
A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration	34
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing	34
A 1920 × 1080 Array 2-D/3-D Image Sensor With 3-μ s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel	33
Guest Editorial Introduction to the Special Section on the 2025 RFIC Symposium	33
New Associate Editor	33
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS	33
Table of Contents	33
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications	33
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs	33
A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer	33
Introducing IEEE Collabratec	33
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications	32
New Associate Editor	32
IEEE Journal of Solid-State Circuits Publication Information	32
Table of Contents	32
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS	32
A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD	31
A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking	31
An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators	31
A 4.6-GHz 54.5-fs _rms PLL-XO Co-Design Featuring a Pulse-Injection XO Driver	31
Space-Mate: A 303.5-mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing	31
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging	31
A 6.5-pJ/Step Reconfigurable Readout IC With Duty-Cycled Resistor and Switched Capacitor for High Linearity RC-to-Digital Converter	31
A Sub-Threshold Oscillator-Based High-Accuracy Temperature Sensor With Tolerance to Supply Fluctuation and Device Aging	31
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm³ Field of View	31
A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail	31
A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT	31
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing	30
Optically Synchronized Phased Arrays in CMOS	30
A 2.5–20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery	30
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications	30
Introducing IEEE Collabratec	30
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing	30
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS	30
TechRxiv: Share Your Preprint Research With the World!	30
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation	30
A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and −100 dBc IM3 for a Mixer-Less DAB Band III Receiver	29
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging	29
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC	29
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS	29
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications	29
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology	29
A High-Resolution Solid-State LiDAR Sensor With Reconfigurable Histogramming Time-to-Digital Converter and Filter for Depth Refinement	29
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation	29
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces	29
A 56-GHz Fractional-N PLL With 110-fs Jitter	29
An Energy-Efficient and High-Accuracy Dual-ModeECG AI Processor via Deep-Fold and Zero-Free Fine-Grained Quantization	29
An 18.3- μ W 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique	28
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS	28
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement	28
A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz	28
A 0.8-V BJT-Based Temperature Sensor With an Inaccuracy of ±0.4 °C (3σ) From −40 °C to 125 °C in 22-nm CMOS	28
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity	28
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier	28
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer	28
A 1.5–23.5-GHz 150.5-Gb/s Distributed PA Using High-Power-Density Cells and Broadband Power Combining Techniques in 40-nm CMOS	28
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications	27
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing	27
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium	27
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features	27
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme	27
A 124–161 GHz Active Vector Modulator for 6G Applications Utilizing a Dual Current Steering With Low RMS Phase and Gain Errors	27

An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation	27
New Associate Editor	27
TechRxiv: Share Your Preprint Research with the World!	27
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC)	26
A Recursive N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting	26
A Constant Bandwidth Oversampling PLL Enabled by a Constant-Gain Oversampler Composed of Double-Edge and Sampling Single-Edge Capacitive Charging and Discharging Phase Interpolators	26
Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications	26
A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping	26
A 3.1- μ W Analog-Assisted Zoom Histogramming TDC in 35- μ m Pixel Pitch for Flash LiDAR Sensor	26
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection	26
A 0.00175 mm ² and 9.62 μ W per Channel Direct-Digitization Front End With EDO Compensation for Neural	26
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback	26
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI	26
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces	26
An Edge 3-D Gaussian Splatting Processor Based on Shape-Aware Computation Architecture and Spatio-Temporal Gaussian Cache	26
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement	25
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL	25
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology	25
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques	25
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive	25
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit	25
Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning	25
A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 °C to 165 °C Consuming 210 μW at 70 MHz	25
A 28-nm RRAM/SRAM Collaborative CIM Accelerator Supporting RRAM-Endurance-Latency Awareness for Edge Fine-Tuning	25
A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition	25
Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS	25
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm	24
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI	24
A 4.9–7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application	24
A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration	24
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification	24
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS	24
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS	24
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation	24
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient	24
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage	24
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking	24
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range	24
A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application	24
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving −28.5-dBm Sensitivity	24
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC	24
IEEE JOURNAL OF SOLID-STATE CIRCUITS	24
A Dual-Band Simultaneous RF Energy Harvesting System With Globally Optimized 3-D MPPT and Efficiency Enhancement	24
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS	24
TechRxiv: Share Your Preprint Research With the World!	23
Table of Contents	23
Introducing IEEE Collabratec	23
New Associate Editor	23
New Associate Editor	23
Table of Contents	23
IEEE Journal of Solid-State Circuits Information for Authors	23
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium	23
TechRxiv: Share Your Preprint Research With the World!	23
TechRxiv: Share Your Preprint Research with the World!	23
IEEE Journal of Solid-State Circuits Publication Information	23
A 136.6-dB-DR 174.3-dB-FoM _S Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop	22
A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET	22
A 2.2-ps Time-of-Flight Resolution Frequency-Domain fNIRS Readout IC With a Dynamic Architecture and Cross-Coupling-Free Intensity and Phase-to-Digital Converter	22
A 48–56 GHz >1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna	22
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security	22
New Associate Editor	22
Table of Contents	22
A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector	22
TechRxiv: Share Your Preprint Research With the World!	22
NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core	22
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack Depth Sensing	22
A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically-Switching Passive Body Channel Communication	22
Table of Contents	22
A 20-Gb/s/Line Single-Ended Transceiver With Coupling-Balanced Crosstalk-Cancellation for Shield-Less 1.5- μ m-Pitch Interconnect	22
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy	22
An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation	22
A Six-Phase Harmonic-Rejection Digital Transmitter	22
Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”	22
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction	22
Planar 200-GHz Transceiver Modules	22
A 0.033-mm² 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF	21
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration	21
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting	21
Sub-Terahertz Wideband ASK Transceiver for 14/27/64 Gb/s 0.27-km/0.12-m/0.1-mm Interconnection in 28-nm CMOS	21
A 200-GHz Power Amplifier With 18.7-dBm P _sat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification	21
A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems	21
A 28-GHz, Multi-Beam, Decentralized Relay Array	21
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS	21
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond	21
A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration	21
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS	21
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM	21
Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium	20
IEEE Journal of Solid-State Circuits Information for Authors	20
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application	20
New Associate Editor	20
A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing	20
IEEE Journal of Solid-State Circuits Information for Authors	20
Introducing IEEE Collabratec	20
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks	20