IEEE Journal of Solid-State Circuits

Article	Citations
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism	160
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS	136
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing	95
300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers	94
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR	89
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS	89
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation	81
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration	73
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks	71
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons	68
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips	61
A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers	56
A 20-GHz 1.9-mW LNA Using g m-Boost and Current-Reuse Techniques in 65-nm CMOS for Satellite Communications	56
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects	55
High-Value Tunable Pseudo-Resistors Design	55
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors	55
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture	54
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management	54
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier	54
A 24.5–43.5-GHz Ultra-Compact CMOS Receiver Front End With Calibration-Free Instantaneous Full-Band Image Rejection for Multiband 5G Massive MIMO	54
HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs	52
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control	52
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions	51
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices	51
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference	50

A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording	50
A 1.7-dB Minimum NF, 22–32-GHz Low-Noise Feedback Amplifier With Multistage Noise Matching in 22-nm FD-SOI CMOS	49
Design and Analysis of Enhanced Mixer-First Receivers Achieving 40-dB/decade RF Selectivity	49
A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse	49
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET	48
A 0.46-THz 25-Element Scalable and Wideband Radiator Array With Optimized Lens Integration in 65-nm CMOS	47
A Coupler-Based Differential mm-Wave Doherty Power Amplifier With Impedance Inverting and Scaling Baluns	47
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems	47
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking	44
Analysis and Design of a 260-MHz RF Bandwidth +22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA	44
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS	44
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS	43
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode	43
Track-and-Zoom Neural Analog-to-Digital Converter With Blind Stimulation Artifact Rejection	42
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting	42
Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning	41
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems	41
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO	41
A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2:1 Analog Multiplexer in 250-nm InP DHBT	40
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction	39
A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications	39
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching	39
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter	39
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference	38
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports	38
A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer	38
A 128 × 128 SPAD Motion-Triggered Time-of-Flight Image Sensor With In-Pixel Histogram and Column-Parallel Vision Processor	38
A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology	38
A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging	38
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition	37
A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications	37
A Reconfigurable Hybrid Series/Parallel Doherty Power Amplifier With Antenna VSWR Resilient Performance for MIMO Arrays	37
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation	36
11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors	36
A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design	36
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion	35
A Batteryless Motion-Adaptive Heartbeat Detection System-on-Chip Powered by Human Body Heat	34
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference	34
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices	34
A 2-in-1 Temperature and Humidity Sensor With a Single FLL Wheatstone-Bridge Front-End	34
A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization	33
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation	33
A 22.3-nW, 4.55 cm2 Temperature-Robust Wake-Up Receiver Achieving a Sensitivity of −69.5 dBm at 9 GHz	33
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source	33
Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers	33
A 32 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate	32
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS	31
A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation	31
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks	31
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension	31

A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement	31
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier	31
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration	30
A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz	30
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength	30
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps	30
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers	30
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation	30
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS	30
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond	30
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation	29
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW	29
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks	29
A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS	29
A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System	29
A Wideband Low-Power Cryogenic CMOS Circulator for Quantum Applications	29
Structure-Reconfigurable Power Amplifier (SR-PA) and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System	29
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression	28
A High-Power Broadband Multi-Primary DAT-Based Doherty Power Amplifier for mm-Wave 5G Applications	28
THz Prism: One-Shot Simultaneous Localization of Multiple Wireless Nodes With Leaky-Wave THz Antennas and Transceivers in CMOS	28
A 64-Channel Transmit Beamformer With ±30-V Bipolar High-Voltage Pulsers for Catheter-Based Ultrasound Probes	28
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement	28
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications	27
2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter	27
Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression	27
A 64-Pixel 0.42-THz Source SoC With Spatial Modulation Diversity for Computational Imaging	27
A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency	26
High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5–19-dBm Psat and 14.2–12.1% Peak PAE in 45-nm CMOS RFSOI	26
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode	26
A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting	26
A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS	26
An Eight-Element 140-GHz Wafer-Scale IF Beamforming Phased-Array Receiver With 64-QAM Operation in CMOS RFSOI	26
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip	26
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection	26
A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio	26
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS	25
Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit	25
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication	25
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition	25
Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer	25
A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS	25
A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW	25
A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS	25
A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs	24
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing	24
First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth	24
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission	24
A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes	24
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC	24
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding	24
A 22-ng/$\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques	24
A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit	24
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme	24
Octave-Tuning Dual-Core Folded VCO Leveraging a Triple-Mode Switch-Less Tertiary Magnetic Loop	24
A High-Efficiency 142–182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-Based Power Combining Technique	24
Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications	24
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR	24
The Design of a CMOS Nanoelectrode Array With 4096 Current-Clamp/Voltage-Clamp Amplifiers for Intracellular Recording/Stimulation of Mammalian Neurons	24
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS	24
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer	24
Extracellular Recording of Entire Neural Networks Using a Dual-Mode Microelectrode Array With 19 584 Electrodes and High SNR	23
A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS	23
A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation	23
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration	23
High-Voltage CMOS Active Pixel Sensor	23
A 0.35-V 5,200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator	23
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing	23
Direct 12V/24V-to-1V Tri-State Double Step-Down Power Converter With Online V CF Rebalancing and In-Situ Precharge Rate Regulation	23
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References	22
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications	22
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion	22
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing	22
Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance	22
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P sat for 5G NR FR2 Operation	22
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation	22
A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off	22
Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency	22
Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS	22
An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs	22
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits	22

A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error	22
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain	22
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver	22
Low-Power Organic Light Sensor Array Based on Active-Matrix Common-Gate Transimpedance Amplifier on Foil for Imaging Applications	22
A 1.8-nW, −73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes	22
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface	22
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation	21
A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application	21
NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC	21
An Interference-Resilient BLE-Compatible Wake-Up Receiver Employing Single-Die Multi-Channel FBAR-Based Filtering and a 4-D Wake-Up Signature	21
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips	21
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation	21
A Hybrid Boost Converter With Cross-Connected Flying Capacitors	21
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy	21
A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA	21
A Low-Power 70–100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback	21
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS	21
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning and Online Tuning	21
Low-Loss Heterogeneous Integrations With High Output Power Radar Applications at W-Band	20
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET	20
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback	20
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution	20
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter	20
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links	20
Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS	20
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference	20
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse	20
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection	20
A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT	20
An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation ASIC	20
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction	20
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode	20
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing	19
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion	19
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS	19
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry	19
A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing	19
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS	19
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter	19
A 43–97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection	19
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices	19
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping	19
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture	19
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS	19
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link	19
Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s	19
A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation	19
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and V SW Dual-Edge Dead-Time Modulation Techniques	19
A 420-GHz Sub-5-μm Range Resolution TX–RX Phase Imaging System in 40-nm CMOS Technology	18
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network	18
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications	18
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers	18
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator	18
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples	18
A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs	18
A Ka-Band Doherty-Like LMBA for High-Speed Wireless Communication in 28-nm CMOS	18
50nW Opamp-Less ΔΣ-Modulated Bioimpedance Spectrum Analyzer for Electrochemical Brain Interfacing	18
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing	18
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security	18
Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic Drug Monitoring	18
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator	18
A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC	17
Integrated Self-Adaptive and Power-Scalable Wideband Interference Cancellation for Full-Duplex MIMO Wireless	17
Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator	17
Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability	17
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement	17
Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density	17
A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment	17
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme	17
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process	17
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs	17
An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves	17
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices	17
A 24–30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas	17
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS	17
A Dual-Mode Wi-Fi/BLE Wake-Up Receiver	17
A 16.1-bit Resolution 0.064-mm2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS	17
A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications	17
A 1-nA 4.5-nW 289-ppm/°C Current Reference Using Automatic Calibration	17
A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD	17
A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole	17
A 12.3-μW 0.72-mm² Fully Integrated Front-End IC for Arterial Pulse Waveform and ExG Recording	17
A 220-GHz Energy-Efficient High-Data-Rate Wireless ASK Transmitter Array	17
A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting	17
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture	17
A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter	17
An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation	17
Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting	16
Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting	16
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS	16
Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers	16
A Low-Power Backscatter Modulation System Communicating Across Tens of Meters With Standards-Compliant Wi-Fi Transceivers	16
A Time-Interleaved Resonant Voltage Mode Wireless Power Receiver With Delay-Based Tracking Loops for Implantable Medical Devices	16
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator	16
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning	16