OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Journal of Solid-State Circuits is 11. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC–DC Converters	113
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel	91
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	89
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	84
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	81
A mm-Wave Switched-Capacitor RFDAC	80
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	72
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	68
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	65
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ^∘C (3σ) Inaccuracy From -55 ^∘C to 125 ^∘C	62
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	62
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	61
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	61
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication	61
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	60
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	59
Table of Contents	58
IEEE JOURNAL OF SOLID-STATE CIRCUITS	57
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier	56
Message From the Incoming Editor-in-Chief	56
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports	54
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer	53
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-$\mu$s Retention Time	53
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	52
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators	51

Table of Contents	50
IEEE JOURNAL OF SOLID-STATE CIRCUITS	50
NeuroFlare: An mm³-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	49
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS	48
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	48
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P _sat for 5G NR FR2 Operation	47
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting	46
Table of Contents	45
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	45
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	45
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode	44
Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur	44
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode	43
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver	43
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory	43
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology	43
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS	43
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead	42
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion	42
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI	42
Information For Authors	41
RFIC 2023 Call for Papers	41
Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode	40
IEEE JOURNAL OF SOLID-STATE CIRCUITS	40
Analysis and Design of a 10.4-ENOB 0.92–5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications	40
Table of Contents	40
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET	40
Table of Contents	40
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation	39
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing	39
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS	39
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC	38
Realization of In-Band Full-Duplex Operation at 300 and 4.2 K Using Bilateral Single-Sideband Frequency Conversion	38
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors	38
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM	37
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology	37
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference	37
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs	37
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level	37
Table of Contents	37
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing	37
TechRxiv: Share Your Preprint Research With the World!	36
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers	35
A Bidirectional USB Power Delivery Voltage-Regulating Cable	35
Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance	35
Table of Contents	35
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET	35
An 85-GHz Power Amplifier Utilizing a Transformer-Based Power Combiner Operating Beyond the Self-Resonance Frequency	34
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers	34
Erratum to “A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain” [Nov 21 3360-3374]	34

A Fully Energy-Autonomous Temperature-to-Time Converter Powered by a Triboelectric Energy Harvester for Biomedical Applications	34
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS	34
A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout	34
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium	33
New Associate Editor	33
On-Chip Condition-Adaptive Δ f ³ EMI Control for Switching Power ICs	33
TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration	33
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip	33
A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI	33
A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics	33
76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications	33
New Associate Editor	32
A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing	32
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation	32
A 1920 $\times$ 1080 Array 2-D/3-D Image Sensor With 3-$\mu$s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel	32
A Single Li-Ion Battery Powered Buck Converter With >90% Efficiency Over 10-μA to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology	31
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS	31
Table of Contents	31
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application	31
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications	31
A 22-nm Delta–Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing	31
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications	31
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity	30
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging	30
A 6-GHz Continuous-Time Bandpass TEXPRESERVE0 ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver	30
A 0.35-V 5,200-μm² 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator	30
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm³ Field of View	30
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology	29
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features	29
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces	29
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture	29
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS	29
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS	29
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing	29
An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation	29
A Full-Duplex Rake Receiver Using RF Code-Domain Signal Processing for Multipath Environments	28
A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD	28
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction	28
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement	28
Introducing IEEE Collabratec	28
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier	28
Table of Contents	28
Design and Characterization of a 10-MHz GaN Gate Driver Using On-Chip Feed-Forward Gaussian Switching Regulation for EMI Reduction	28
New Associate Editor	28
A 2.5–20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery	27
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source	27
A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC	27
A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking	27
A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz	27
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer	26
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging	26
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation	26
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique	26
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications	26
New Associate Editor	26
A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail	26
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS	26
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS	26
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing	26
Optically Synchronized Phased Arrays in CMOS	26
An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With −93-dB THD+N, 113-dB SNR, and 93% Efficiency	26
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC	25
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS	25
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing	25
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver	25
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme	25
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation	25
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications	25
A 56-GHz Fractional-N PLL With 110-fs Jitter	25
A 0.8-V BJT-Based Temperature Sensor With an Inaccuracy of ±0.4 °C (3σ) From −40 °C to 125 °C in 22-nm CMOS	25
TechRxiv: Share Your Preprint Research With the World!	25
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification	24
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation	24
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium	24
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range	24
A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation	24
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS	24
2021 Index IEEE Journal of Solid-State Circuits Vol. 56	24
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End	24
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction	24

A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking	24
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	24
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips	24
TechRxiv: Share Your Preprint Research with the World!	24
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving $-$28.5-dBm Sensitivity	24
A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 °C to 165 °C Consuming 210 μW at 70 MHz	24
Erratum to “A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System-on-Chip”	24
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback	24
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques	23
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer	23
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification	23
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage	23
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive	23
A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping	22
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm	22
A 0.00175 mm² and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm	22
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS	22
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation	22
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL	22
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit	22
A 4.9–7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application	22
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL	22
New Associate Editor	22
A Recursive N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting	22
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques	22
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS	22
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement	22
Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning	22
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI	22
Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications	22
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection	21
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology	21
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient	21
TechRxiv: Share Your Preprint Research with the World!	21
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security	21
A 420-GHz Sub-5-μm Range Resolution TX–RX Phase Imaging System in 40-nm CMOS Technology	21
A Self-Calibrated Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor	21
A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration	21
TechRxiv: Share Your Preprint Research With the World!	21
New Associate Editor	21
Table of Contents	21
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mmTEXPRESERVE0 Density in 28nm CMOS	21
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC	21
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces	21
IEEE JOURNAL OF SOLID-STATE CIRCUITS	21
TechRxiv: Share Your Preprint Research With the World!	21
A 3.1-$\mu$W Analog-Assisted Zoom Histogramming TDC in 35-$\mu$m Pixel Pitch for Flash LiDAR Sensor	21
TechRxiv: Share Your Preprint Research with the World!	20
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset	20
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting	20
Table of Contents	20
Information For Authors	20
Table of Contents	20
First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth	20
Table of Contents	20
Introducing IEEE Collabratec	20
Planar 200-GHz Transceiver Modules	20
New Associate Editor	20
IEEE JOURNAL OF SOLID-STATE CIRCUITS	20
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy	19
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack Depth Sensing	19
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond	19
New Associate Editor	19
A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection Crystal Oscillator	19
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM	19
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations	19
A 2.46-mm² Miniaturized Brain-Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding	19
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL	19
A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter	19
A 48–56 GHz $>$1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna	19
A 28-GHz, Multi-Beam, Decentralized Relay Array	19
IEEE Journal of Solid-State Circuits Publication Information	19
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR	19
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets	19
Erratum to “A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver”	19
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium	19
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines	19
An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation	19
A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS	19
IEEE Journal of Solid-State Circuits Information for Authors	19
A 200-GHz Power Amplifier With 18.7-dBm P _sat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification	19
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS	18
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration	18
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application	18
Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56fmax: An Analytical Approach on Reversed Feedback Amplifiers	18
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays	18
Ultra-Wideband Switched-Capacitor Delays and Circulators—Theory and Implementation	18
A 2.2-ps Time-of-Flight Resolution Frequency-Domain fNIRS Readout IC With a Dynamic Architecture and Cross-Coupling-Free Intensity and Phase-to-Digital Converter	18
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS	18
A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction	18
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks	18
A Six-Phase Harmonic-Rejection Digital Transmitter	18
A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration	18
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection	18
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction	18