IEEE Transactions on Computers

Papers
(The H4-Index of IEEE Transactions on Computers is 36. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)
ArticleCitations
DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures236
NetMod: Toward Accelerating Cloud RAN Distributed Unit Modulation Within Programmable Switches118
Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation118
Redactable Blockchain From Decentralized Chameleon Hash Functions, Revisited102
Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications100
Exploring Hyperdimensional Computing Robustness Against Hardware Errors91
A Machine Learning-Empowered Cache Management Scheme for High-Performance SSDs86
Secure Deep Learning in Defense in Deep-Learning-as-a-Service Computing Systems in Digital Twins82
Affinity-Aware VNF Placement in Mobile Edge Clouds via Leveraging GPUs80
The Butterfly Effect in Primary Visual Cortex80
Energy-Delay-Aware Joint Microservice Deployment and Request Routing with DVFS in Edge: A Reinforcement Learning Approach79
A Complexity-Effective Local Delta Prefetcher76
Guest Editorial: IEEE Transactions on Computer, Special Issue on Hardware Security73
Brain-Inspired Computing for Circuit Reliability Characterization63
Blockchain-Based Distributed Multiagent Reinforcement Learning for Collaborative Multiobject Tracking Framework62
Deep Learning Operators Performance Tuning for Changeable Sized Input Data on Tensor Accelerate Hardware60
A Systematic View of Model Leakage Risks in Deep Neural Network Systems57
Online Scheduling of Distributed Machine Learning Jobs for Incentivizing Sharing in Multi-Tenant Systems57
nDirect2: A High-Performance Library for Direct Convolutions on Multi-Core CPUs54
ReViT: Vision Transformer Accelerator With Reconfigurable Semantic-Aware Differential Attention54
Dynamic Graph Publication with Differential Privacy Guarantees for Decentralized Applications52
Distributed Sketch Deployment for Software Switches48
WaWoT: Towards Flexible and Efficient Web of Things Services via WebAssembly on Resource-Constrained IoT Devices48
A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing47
Hierarchical Hashing: A Dynamic Hashing Method With Low Write Amplification and High Performance for Non-Volatile Memory46
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems45
Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency45
Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash45
Scenario-based AI Benchmark Evaluation of Distributed Cloud/Edge Computing Systems42
Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks40
A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices39
Wrong-Path-Aware Entangling Instruction Prefetcher39
On Key–Value Sort With Active Compute Memory38
Distributed Learning for Large-Scale Models at Edge With Privacy Protection38
HiBid: A Cross-Channel Constrained Bidding System With Budget Allocation by Hierarchical Offline Deep Reinforcement Learning36
Breaking the DECT Standard Cipher With Lower Time Cost36
BFT-DSN: A Byzantine Fault-Tolerant Decentralized Storage Network36
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