IEEE Transactions on Computers

Papers
(The H4-Index of IEEE Transactions on Computers is 33. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-11-01 to 2025-11-01.)
ArticleCitations
CROSC: Compilation-Runtime Joint Optimization for Fast Smart Contract Execution184
Redactable Blockchain From Decentralized Chameleon Hash Functions, Revisited127
A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing121
Online Scheduling of Distributed Machine Learning Jobs for Incentivizing Sharing in Multi-Tenant Systems111
WaWoT: Towards Flexible and Efficient Web of Things Services via WebAssembly on Resource-Constrained IoT Devices103
Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems101
Analysis & Design of Convolution Operator for High Speed and High Accuracy Convolutional Neural Network-Based Inference Engines94
Meta-Block: Exploiting Cross-Layer and Direct Storage Access for Decentralized Blockchain Storage Systems81
SSD In-Storage Computing for Search Engines71
Extending Performance-Energy Trade-offs Via Dynamic Core Scaling71
UKFaaS: Lightweight, High-Performance and Secure FaaS Communication With Unikernel70
ParBFT: An Optimized Byzantine Consensus Parallelism Scheme68
RSQC: Recursive Sparse QUBO Construction for Quantum Annealing Machines67
MMDataLoader: Reusing Preprocessed Data Among Concurrent Model Training Tasks65
How to Launch a Powerful Side-Channel Collision Attack?63
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems62
Cost-Efficient Delay-Bounded Dependent Task Offloading With Service Caching at Edges58
Energy-Delay-Aware Joint Microservice Deployment and Request Routing With DVFS in Edge: A Reinforcement Learning Approach54
An Edge-Side Real-Time Video Analytics System With Dual Computing Resource Control53
Analytical Model for Memory-Centric High Level Synthesis-Generated Applications53
Efficient CP-ABE Scheme With Shared Decryption in Cloud Storage51
A Provably Secure Strong PUF Based on LWE: Construction and Implementation50
Tolerance of Siamese Networks (SNs) to Memory Errors: Analysis and Design48
GATe: Efficient Graph Attention Network Acceleration With Near-Memory Processing47
RO(SE)2: Search-Efficient Robust Searchable Encryption With Forward and Backward Security44
Unsupervised Spiking Instance Segmentation on Event Data Using STDP Features41
NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models40
An Energy-Efficient and Privacy-Aware MEC-Enabled IoMT Health Monitoring System39
RTSA: A Run-Through Sparse Attention Framework for Video Transformer38
PCB Hardware Trojan Run-Time Detection Through Machine Learning37
LUNA-CiM: A Programmable Compute-in-Memory Fabric for Neural Network Acceleration35
ElasticEC: Achieving Fast and Elastic Redundancy Transitioning in Erasure-Coded Clusters35
Effective Huge Page Strategies for TLB Miss Reduction in Nested Virtualization33
Karatsuba Matrix Multiplication and Its Efficient Custom Hardware Implementations33
Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements33
Raptor-T: A Fused and Memory-Efficient Sparse Transformer for Long and Variable-Length Sequences33
A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress33
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