Integration-The VLSI Journal

Papers
(The H4-Index of Integration-The VLSI Journal is 23. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
A high reliability under-voltage lock out circuit for power driver IC118
Generating pseudo-random numbers with a Brownian system86
Model of a switched-capacitor programmable voltage reference for ultra low-power applications82
Dynamics analysis and application of multi-stable Hopfield neural networks under pulsed current stimulation65
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults51
Enhancing logic optimization of Alliance tool based on directed acyclic graphs51
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems49
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer48
Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system47
A sub-1V wide-temperature-range voltage reference with low line sensitivity and high temperature stability45
Real-time FPGA implementation of a blind audio watermarking scheme based on discrete cosine transform and improved spread spectrum45
An adaptive discrete dynamic filled function algorithm for directed acyclic graph partitioning43
An absolute capacitive rotary encoder with DC offset correction capacitor arrays41
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips39
Chaos based speech encryption using microcontroller33
A general and accurate pattern search method for various scenarios30
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application30
Efficient processor verification by tautologies-derived universal properties model checking26
HDLBC: A lightweight block cipher with high diffusion26
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism26
Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA25
An LA-group based design of the non-linear component of block cipher24
A transparent virtual channel power gating method for on-chip network routers24
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding23
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