Integration-The VLSI Journal

Article	Citations
Editorial Board	98
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	97
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	61
A high reliability under-voltage lock out circuit for power driver IC	49
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	46
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	43
Generating pseudo-random numbers with a Brownian system	37
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	34
Chaos based speech encryption using microcontroller	34
Edge computing design space exploration for heart rate monitoring	34
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	33
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	33
A general and accurate pattern search method for various scenarios	31
mMIG: Inversion optimization in majority inverter graph with minority operations	28
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	26
A transparent virtual channel power gating method for on-chip network routers	24
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	24
Design of high-efficiency complex multiplier for fault-tolerant computation	23
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	23
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	22
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	22
Design and application of multiscroll chaotic attractors based on memristors	22
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	20
An LA-group based design of the non-linear component of block cipher	19
HDLBC: A lightweight block cipher with high diffusion	19

Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	19
High-Robustness CMOS Voltage Reference for Automotive Applications with PVT Variation Tolerance	18
Synchronization of mutual coupled fractional order one-sided lipschitz systems	17
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	17
Design and implementation of congestion aware router for network-on-chip	17
FPGA-based implementation of classification techniques: A survey	17
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	17
Efficient design of decimation filter using linear programming and its FPGA implementation	16
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	16
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	16
Design of Flash analog-to-digital converter based on MoS2 FET	15
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	15
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	15
Low power chaotic oscillator employing CMOS	15
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS	14
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	14
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	14
Matching constraint extraction for analog integrated circuits layout via edge classify	14
Simple memristive chaotic systems with complex dynamics	14
Clock mesh synthesis through dynamic programming with physical parameters consideration	14
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	14
Design of novel low cost triple-node-upset self-recoverable hardened latch	13
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	12
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	12
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	12
Design of robust analog integrated circuit based on process corner performance variability minimization	12
An improved algorithm for accelerating reconfiguration of VLSI array	12
A new low-power Dynamic-GDI full adder in CNFET technology	11
Hyperchaotic fractional Grassi–Miller map and its hardware implementation	11
Neurochaos feature transformation for Machine Learning	11
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	11
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	11
Differential receiver with 2 × VDD input signals using 1 × VDD devices	11
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	10
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	10
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	10
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	10
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	10
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	10
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	10
Alternative method to reveal encoded images via Gaussian distribution functions	10
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	10
Hot-spot aware thermoelectric array based cooling for multicore processors	10
Editorial Board	10
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	10
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	10
An improved reconfigurable logic in resistive random access memory	10
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	10
Third-order resonance networks and their application to chaos generation	10
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH)	10

Editorial Board	10
A simulation optimization method for Verilog-AMS IBIS model under overclocking	10
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	9
Fixed-point implementations for feed-forward artificial neural networks	9
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	9
AI/ML algorithms and applications in VLSI design and technology	9
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	9
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	9
Editorial Board	9
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	9
Intelligent and kernelized placement: A survey	9
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	9
Editorial Board	9
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	8
A secure scan architecture using parallel latch-based lock	8
Editorial Board	8
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	8
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	8
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	8
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	7
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	7
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	7
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	7
Electronic equivalent of a pump-modulated erbium-doped fiber laser	7
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	7
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	7
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	7
On-board processing for autonomous drone racing: An overview	7
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	7
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	7
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	7
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	7
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	7
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	7
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	7
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	7
Optimizing code allocation for hybrid on-chip memory in IoT systems	7
Automatic correction of RTL designs using a lightweight partial high level synthesis	6
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	6
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	6
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	6
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	6
A hybrid memory polynomial digital predistortion model for RF transmitters	6
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	6
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	6
Neural network ℒ1	6
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	6
High-resolution calibrated successive-approximation-register analog-to-digital converter	6
Language semantics to support secure computation and communication in embedded systems via hardware monitors	6
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	6
Approximate squaring circuits exploiting recursive architectures	6
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	6
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	6
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	6
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	6
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	6
A broadband MVDR beamforming core for ultrasound imaging	6
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	6
VLFF — A very low-power flip-flop with only two clock transistors	6
Editorial Board	6
Lorenz system as a filter	6
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	6
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	6
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	6
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance	5
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
Chosen ciphertext correlation power analysis on Kyber	5
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	5
An efficient image encryption scheme based on double affine substitution box and chaotic system	5
Hardware design for blind source separation using fast time-frequency mask technique	5
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	5
Intra-class CutMix data augmentation based deep learning side channel attacks	5
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	5
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)	5
BonnLogic: Delay optimization by And-Or Path restructuring	5
Editorial Board	5
A high-efficiency feedforward compensation method for capacitor-less LDO	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5

A frequency boosting technique for cold-start charge pump units	5
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	5
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging	5
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons	5
156 dB low-voltage low-power CMOS exponential function generator circuit	5
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network	5
A fast and high-performance global router with enhanced congestion control	5
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end	5
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	5
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	5
Integrated DC - DC converter design methodology for design cycle speed up	5
A low power offset voltage calibration method for flash ADCs	5
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	5
Compact MAX and MIN Stochastic Computing architectures	5
Design and implementation of deep learning-based object detection and tracking system	4
Reference-free power supply monitor with enhanced robustness against process and temperature variations	4
Real-time infrared small target detection network and accelerator design	4
A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS	4
A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction	4
Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map	4
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	4
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	4
CCTA based four different pairs of mutually coupled circuit using single topology	4
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications	4
Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis	4
A novel on-chip linear and switching mixed regulation against power analysis attacks	4
A wide-output buck DC-DC power management IC	4
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems	4
Comparative study of planar stacked integrated transformers for MMICs	4
Radiation-aware analog circuit design via fully-automated simulation environment	4
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	4
Enhanced FPGA implementation of Echo State Networks for chaotic time series prediction	4
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation	4
Design of FIR filter ISOTA with the aid of genetic algorithm	4
Artificial synapse topologies using arbitrary-order memristors	4
Reliability-aware design of Integrate-and-Fire silicon neurons	4
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design	4
LA-ring based non-linear components: Application to image security	4
Editorial Board	4
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection	3
Scalable layout decomposition implemented by a distribution evolutionary algorithm	3
Optimizing machine learning logic circuits with constant signal propagation	3
The art of temporal decoupling	3
Efficient VLSI architecture of 3D discrete transformation	3
Grammar-based fuzz testing for microprocessor RTL design	3
Dynamics analysis, FPGA implementation, and application in image encryption of a quadruple-wing chaotic system based on hyperbolic sine functions	3
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network	3
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	3
Editorial Board	3
A robust radiation resistant SRAM cell for space and military applications	3
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA	3
WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed	3
A new die-level flexible design-for-test architecture for 3D stacked ICs	3
Lorenz’s state equations as RC filters	3
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells	3
A compact structure for triple-memristor maps with a hyperplane of fixed points	3
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements	3
SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application	3
An aging monitoring scheme for SRAM decoders	3
Editorial Board	3
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	3
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations	3
SAND-2: An optimized implementation of lightweight block cipher	3
A chaotic PRNG tested with the heuristic Differential Evolution	3
A novel current-controlled memristor-based chaotic circuit	3
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support	3
Design and implementation of filterbank for MPEG-2/4 AAC system	3
DULBC: A dynamic ultra-lightweight block cipher with high-throughput	3
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	3
New approach for digital calibration of pipelined analog to digital converters based on secant method	3
O.O: Optimized one-die placement for face-to-face bonded 3D ICs	3
BJT induced dark current in CMOS image sensors	3
Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case	3
New partitioned domino circuit for power-efficient wide gates	3
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	3
Mathematical analysis and circuit emulator design of the three-valued memristor	3
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	3
A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier	3
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs	2
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application	2
2×	2
Robust battery lifetime prediction with noisy measurements via total-least-squares regression	2
Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation	2
On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm	2
Optimization on operation sorting for HLS scheduling algorithms	2
Switched pseudo-current mirror inverter for low-power, thermally stable and robust ring oscillator	2
Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology	2
Second-order cascode-based filters	2
A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology	2
FPGA implementation of EEG based hardware optimized data encryption technique for IoT applications	2
Enhancing cell delay accuracy in post-placed netlists using ensemble tree-based algorithms	2
Finding the longest delay paths for the array-form multipliers using a genetic algorithm	2
Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application	2