Integration-The VLSI Journal

Article	Citations
Optimizing code allocation for hybrid on-chip memory in IoT systems	94
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	91
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme	58
Design and implementation of deep learning-based object detection and tracking system	46
Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS	44
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	44
Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter	43
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	35
Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation	31
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	31
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design	27
Editorial Board	25
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults	25
Edge computing design space exploration for heart rate monitoring	23
Editorial Board	22
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications	21
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater	21
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	21
Editorial Board	20
Editorial Board	19
Editorial Board	19
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	19
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications	17
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	17
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	17

Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	17
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	16
Editorial Board	15
Editorial Board	15
Radiation-aware analog circuit design via fully-automated simulation environment	15
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ	15
Qualitative data augmentation for performance prediction in VLSI circuits	15
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology	15
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	14
Design of self-recovering low-cost multiple-node-upset-tolerant latch	14
Electronically tunable positive and negative fractional order inductor circuit using single topology	14
SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources	14
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	14
A non-autonomous chaotic system with no equilibrium	13
Chaos based speech encryption using microcontroller	13
A low offset low power CMOS dynamic comparator for analog to digital converters	13
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	13
Editorial Board	12
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination	12
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset	11
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS	11
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	11
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits	11
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	11
A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting	11
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	11
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps	10
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	10
A high reliability under-voltage lock out circuit for power driver IC	10
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS	10
Design of analog front-end integrated circuit of tactile sensor for human-machine interface	10
A secure scan architecture using parallel latch-based lock	10
Breaking LPA-resistant cryptographic circuits with principal component analysis	10
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	10
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	9
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	9
A rail-to-rail high speed comparator with LVDS output in 0.18-μ	9
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	9
A Machine Learning approach for anomaly detection on the Internet of Things based on Locality-Sensitive Hashing	9
Generating pseudo-random numbers with a Brownian system	9
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	8
Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity	8
On-board processing for autonomous drone racing: An overview	8
Self calibrated cooler-less microbolometer readout architecture	8
APoX-M: Accelerate deep point cloud analysis via adaptive graph construction	8
ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning	8
Learning placement order for constructive floorplanning	8
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	8
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	8
Ensemble learning model for effective thermal simulation of multi-core CPUs	8

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects	8
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process	7
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	7
A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques	7
Innovative feedback approach for high-performance low-voltage current mirror	7
Low power, high speed approximate multiplier for error resilient applications	7
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs	7
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	7
LA-ring based non-linear components: Application to image security	7
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	7
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	7
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool	7
Design and research of grounding current monitoring device for converter transformer core and clamp	7
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	7
A three-stage single-miller CMOS OTA with no lower load capacitor limit	7
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	7
CCTA based four different pairs of mutually coupled circuit using single topology	7
PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST	6
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	6
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	6
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC	6
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	6
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	6
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network	6
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA	6
A mathematical programming method for constructing the shortest interconnection VLSI arrays	6
Vulnerable objects detection for autonomous driving: A review	6
The art of temporal decoupling	6
A compact structure for triple-memristor maps with a hyperplane of fixed points	6
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration	6
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	6
Electronic equivalent of a pump-modulated erbium-doped fiber laser	6
A broadband MVDR beamforming core for ultrasound imaging	6
VLFF — A very low-power flip-flop with only two clock transistors	6
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements	6
Editorial Board	6
TeRa: Ternary and Range based packet classification engine	5
An energy efficient synthesis flow for application specific SoC design	5
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection	5
Optimizing machine learning logic circuits with constant signal propagation	5
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element	5
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	5
High-speed binary coded decimal digit multipliers with multiple error detection	5
An optimal channel coding scheme for high-speed data communication	5
Design of novel SMS4-BSK encryption transmission system	5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems	5
New approach for digital calibration of pipelined analog to digital converters based on secant method	5
High-resolution calibrated successive-approximation-register analog-to-digital converter	5
Automatic correction of RTL designs using a lightweight partial high level synthesis	5
Editorial Board	5
Approximate squaring circuits exploiting recursive architectures	5
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system	5
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure	5
Editorial Board	5
Design and implementation of filterbank for MPEG-2/4 AAC system	5
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network	5
New partitioned domino circuit for power-efficient wide gates	5
Editorial Board	5
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions	5
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	5
Application driven routing for mesh based Network-on-Chip architectures	4
mMIG: Inversion optimization in majority inverter graph with minority operations	4
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	4
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	4
A novel one-equilibrium memristive chaotic system with multi-parameter amplitude modulation and large-scale offset boosting	4
An aging monitoring scheme for SRAM decoders	4
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks	4
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	4
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	4
Design and application of multiscroll chaotic attractors based on memristors	4
Design and implementation of current mode circuit for digital modulation	4
A transparent virtual channel power gating method for on-chip network routers	4
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL	4
Design of high-efficiency complex multiplier for fault-tolerant computation	4
High quality hypergraph partitioning for logic emulation	4
Lorenz system as a filter	4
Efficient VLSI architecture of 3D discrete transformation	4
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic	4
An LA-group based design of the non-linear component of block cipher	4
A robust radiation resistant SRAM cell for space and military applications	4

A memristive chaotic system with rich dynamical behavior and circuit implementation	4
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	4
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity	4
BJT induced dark current in CMOS image sensors	4
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	4
A C-band low-power sub-1volt current-reused multiphase oscillator	4
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA	4