OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 38. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
Table of Contents	130
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	110
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	96
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	94
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	93
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	87
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	82
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	81
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	72
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	70
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	68
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	60
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	60
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	59
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	57
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	55
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	53
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	52
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	50
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	48
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	47
Prism-SSD: A Flexible Storage Interface for SSDs	47
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	47
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators	47
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	44

HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	44
Code Synthesis for Dataflow-Based Embedded Software Design	43
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	42
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	42
Contamination-Aware Synthesis for Programmable Microfluidic Devices	42
General Purpose Deep Learning Accelerator Based on Bit Interleaving	41
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	40
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	40
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	39
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	39
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	39
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression	38
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	38
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	38