OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 33. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	187
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	116
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	92
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	77
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	72
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	70
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	70
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	66
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	65
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	63
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	61
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	56
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	56
Table of Contents	55
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	54
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	52
Prism-SSD: A Flexible Storage Interface for SSDs	50
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	44
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	44
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	42
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	42
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	42
Contamination-Aware Synthesis for Programmable Microfluidic Devices	41
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	37
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	37

DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	36
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	36
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	35
Code Synthesis for Dataflow-Based Embedded Software Design	35
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	34
General Purpose Deep Learning Accelerator Based on Bit Interleaving	34
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	34
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	34
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	33
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	33
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	33