OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 32. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	175
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	127
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	105
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	86
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	70
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	65
Contamination-Aware Synthesis for Programmable Microfluidic Devices	65
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	64
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	62
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	62
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	57
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	56
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	52
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	52
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	52
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	51
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	50
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	49
Table of Contents	47
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	45
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	44
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	41
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	40
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	40
Prism-SSD: A Flexible Storage Interface for SSDs	39

Code Synthesis for Dataflow-Based Embedded Software Design	38
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	37
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	37
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	35
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	35
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	34
General Purpose Deep Learning Accelerator Based on Bit Interleaving	34
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	32
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	32
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	32
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	32