OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 36. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-11-01 to 2025-11-01.)

Article	Citations
Table of Contents	209
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	124
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	105
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	87
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	86
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	81
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	76
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	74
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	68
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	67
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	66
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	65
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	60
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	57
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	52
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	49
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	49
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	49
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	46
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	46
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	44
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	43
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	43
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	42
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	42

A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	41
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	41
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	40
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	39
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	39
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	38
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	38
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	38
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	38
Prism-SSD: A Flexible Storage Interface for SSDs	37
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	36
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	36
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	36
Code Synthesis for Dataflow-Based Embedded Software Design	36