IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Table of Contents	136
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	124
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	119
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	105
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	98
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	96
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	89
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	81
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	78
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	76
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	69
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	66
Contamination-Aware Synthesis for Programmable Microfluidic Devices	65
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	61
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	58
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	57
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	54
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	54
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators	53
VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation	53
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	52
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	51
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	50
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	50
Frequency-Domain Modeling of Interconnects Based on Assemble Neural Network for 3-D Integration	48

Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	48
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	48
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	47
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	46
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	46
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	46
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	46
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	44
CorcPUM++: Enabling Row-Access and Column-Access Cooperation for Fair and Efficient Thread-Level Scientific Computing using Resistive Cross-Point Random-Access Memory	43
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	42
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression	41
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	41
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	41
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	40
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	39
General Purpose Deep Learning Accelerator Based on Bit Interleaving	39
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	39
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training	39
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation	37
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	37
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	36
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	36
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	36
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	35
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	35
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	34
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	34
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	34
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	34
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	33
FPGA Technology Mapping With Adaptive Gate Decomposition	33
On Modeling and Detecting Trojans in Instruction Sets	33
A Markov-Chain Based PUF Using Chain-Block-Obfuscation Mechanism Resisting Machine Learning Attacks with High Uniformity Robustness	33
Board-Level Reliability Evaluation and Optimization of Power MOSFET Module Under Thermal Cycling Conditions	33
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	33
Softm e x : Lightweight Softmax Compute Engines Based on Exponentiation Unit	32
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	31
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	31
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	31
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	31
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	31
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	31
Adaptive Edge Offloading for Image Classification Under Rate Limit	31
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	30
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	30
A Memristor Crossbar-Based Lyapunov Equation Solver	30
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	29
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	29
Xplace: An Extremely Fast and Extensible Placement Framework	29
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	29

CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	29
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	28
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	28
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	28
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	28
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	28
DASA: Distribution-Aware Sparse Attention for Accelerating Diffusion Transformer	28
Hierarchical-ISA Supporting Row-wise Operands for Efficient DNN Computation	27
Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint	27
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	27
DAGSIS: A DAG-Aware MAGIC-Based Synthesis Framework for In-Memory Computing	27
Crosstalk Analysis and Advancements in RDL Interposer Design for High-Speed Channels	27
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution	27
TRAGIC: Test Oracle Generation for ISA Compliance Testing via Large Language Model	27
BLAST: Belling the Black-Hat High-Level Synthesis Tool	26
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	26
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	26
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	26
Efficient Sample Preparation With Fully Programmable Valve Arrays	25
SMT Solver With Hardware Acceleration	25
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	25
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	25
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	25
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	25
FedMT: Multitask Federated Learning With Competitive GPU Resource Sharing	25
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	25
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	25
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	25
SwarmRouter: Obstacle-Avoiding Routing for Droplet Swarms on Active-Matrix Digital Microfluidic Biochips	25
Redistribution Layer Routing for Fan-Out Wafer-Level Packaging Considering Multiple Advanced Design Rules	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	24
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	24
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	24
Similarity-Aware CNN for Efficient Video Recognition at the Edge	24
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	24
HeteroQNN: Enabling Distributed QNN Under Heterogeneous Quantum Devices	24
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	24
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	24
Efficient Static-Driven Integration for Step-Function Transient Simulation	23
Table of Contents	23
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	23
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	23
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	23
VirtualSync+: Timing Optimization With Virtual Synchronization	22
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	22
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	22
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	22
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	22
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	22
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	22
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	22
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	22
A Framework of Automated LC -VCO Design with Physical Layout Based on Reinforcement Learning	21
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	21
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	21
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	21
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	21
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	21
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	21
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	21
Harnessing Unipolar Threshold Switches for Enhanced Rectification	21
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	21
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	21
Modular Functional Test Sequences for Test Compaction	20
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	20
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	20
Computational Performance Bounds Prediction in Quantum Computing With Unstable Noise	20
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	20
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	20
AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization	20
Hardware Security Meets Incomplete Netlists: Insights into Trojan Detection via Structural Reasoning	20
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	20
Lightweight Failure Prediction Algorithms Based on Internal Characteristics of 3-D nand Flash Memory	20
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	20
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	19
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	19

Table of Contents	19
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	19
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	19
Online Reset for Signal Temporal Logic Monitoring	19
NeuroSchedule2.0: A Novel GNN-based Scheduling Method with RL-based Preprocessing Optimization for High-level Synthesis	19
SEM-CLIP 2.0: Precise Zero-/Few-Shot Learning for Nanoscale Defect Detection in SEM Image	19
A Zero-overhead Flow for Security Closure	19
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	19
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	19
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	19
TroLL: Exploiting Structural Similarities Between Logic Locking and Hardware Trojans	19
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	19
A Hybrid Test Scheme for Automotive IC in Multisite Testing	19
Division-Free Four-Way Toom–Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs	18
CirOPT : Toward Effective Combinational Equivalence Checking via Compiler Optimization	18
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	18
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	18
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	18
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	18
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	18
Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-Enhanced Genetic Algorithm-Based Approach	18
Modern Automatic PCB Placement With Complex Constraints	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	18
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	18
MarchGen: A March Sequence Generation Method for Faults With an Arbitrary Number of Operations in RAMs	18
Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm–Hardware Co-Design	18
AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs	18
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	18
Table of Contents	18
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	18
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	17
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	17
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	17
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash	17
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	17
Towards Efficient ECO Automation: Timing and DRCs Concurrent Optimization Using Reinforcement Learning	17
Data-Driven Feature Selection Framework for Approximate Circuit Design	17
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	17
Nested Speculative Execution Attacks via Runahead	17
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	17
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	17
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	17
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	17
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String	17
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips	17
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	17
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	17
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	17
Espresso: Exploiting the Sparsity Property in Brain-Inspired Vision Sensors with Spatiotemporal Ordering	17
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	17
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	16
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	16
TransMap: Transformer-Enhanced Divide-and-Conquer Reinforcement Learning Framework for Efficient CGRA Compilation	16
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	16
Quantum Multi-View Feature Selection With Configurable Kernel Circuits and Adaptive Fusion	16
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	16
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test	16
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	16
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	16
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	16
GARNETT: Graph-based Fast yet Accurate Post-Placement Toggle Rate Prediction Model from RTL without Technology-dependent Logic Synthesis and Placement	16
A Novel MDM-Based Optical Networks-on-Chip With Reliability Analysis	16
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	16
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	16
AsyncGrid: An Intra- and Inter-Layer Asynchronous Hybrid Parallelism System for Responsive Edge LLM Inference	16
Accelerating Real-Valued FFT on CPU-FPGA Platforms	16
Efficient Design Optimization for Diffractive Deep Neural Networks	16
RTCache: An Efficient Remapping Table Cache for NVM Wear-Leveling	16
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	16
NoCFuzzer: Automating NoC Verification in UVM	16
Digitally Assisted Mixed-Signal Circuit Security	15
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	15
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	15
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	15
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation	15
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs	15
Modified Sanathanan-Koerner Algorithm for Efficient Uncertainty Quantification with Rational Polynomial Chaos	15
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits	15
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	15
Multiobjective Coverage Optimization for 3-D Heterogeneous Wireless Sensor Networks	15
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	15
Table of Contents	15
Automated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs	15
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers	15
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	15
Intertwine: Nonlinear Quantum Feature Selection With Multi-Kernel Circuits	15
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	15
Counteracting Adversarial Attacks in Autonomous Driving	15
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	15
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	15
AIoTML: A Unified Modeling Language for AIoT-Based Cyber–Physical Systems	15
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks	15
Toward the Predictability of Dynamic Real-Time DNN Inference	14
Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units	14
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism	14