IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	181
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	114
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	89
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	72
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	70
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	70
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	67
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	65
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	64
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	60
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	59
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	54
Table of Contents	53
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	53
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	52
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	51
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	51
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	50
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	44
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	42
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	42
Prism-SSD: A Flexible Storage Interface for SSDs	41
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	41
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	40
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	38

Code Synthesis for Dataflow-Based Embedded Software Design	37
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	36
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	36
General Purpose Deep Learning Accelerator Based on Bit Interleaving	35
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	34
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	33
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	33
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	33
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	32
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	32
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	32
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	32
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	31
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	31
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	31
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	31
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	31
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	31
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	30
Contamination-Aware Synthesis for Programmable Microfluidic Devices	30
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	29
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	29
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	29
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	28
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	28
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	27
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	27
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	26
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	25
2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40	25
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	25
Efficient Sample Preparation With Fully Programmable Valve Arrays	25
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	25
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	25
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	24
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	24
SMT Solver With Hardware Acceleration	24
Xplace: An Extremely Fast and Extensible Placement Framework	24
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	24
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	23
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	23
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	23
DAGSIS: A DAG-Aware MAGIC based Synthesis Framework for In-Memory Computing	23
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	23
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	23
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	22
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	22

Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	22
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	22
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	22
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	22
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	22
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	22
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	21
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	21
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	21
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	20
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	20
BLAST: Belling the Black-Hat High-Level Synthesis Tool	20
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	20
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	20
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	20
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	20
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults	20
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	19
FPGA Technology Mapping With Adaptive Gate Decomposition	19
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	19
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices	19
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	19
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	19
A Memristor Crossbar-Based Lyapunov Equation Solver	19
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	19
On Modeling and Detecting Trojans in Instruction Sets	19
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	19
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive	18
Table of Contents	18
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	18
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	18
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	18
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	18
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	18
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	18
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	18
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	18
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	18
Adaptive Edge Offloading for Image Classification Under Rate Limit	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	18
Similarity-Aware CNN for Efficient Video Recognition at the Edge	18
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	18
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	18
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	18
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	17
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	17
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling	17
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	17
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	17
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	17
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor	17
Harnessing Unipolar Threshold Switches for Enhanced Rectification	17
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	17
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	17
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	16
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	16
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds	16
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	16
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	16
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL	16
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	16
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	16
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	16
VirtualSync+: Timing Optimization With Virtual Synchronization	16
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	16
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	16
Efficient Static-Driven Integration for Step-Function Transient Simulation	16
Online Reset for Signal Temporal Logic Monitoring	16
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	16
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	16
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	16
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	16
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority	16
Efficient Design Optimization for Diffractive Deep Neural Networks	15
A Hybrid Test Scheme for Automotive IC in Multisite Testing	15
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	15
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	15
Table of Contents	15
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	15

Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	15
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	15
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	15
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	15
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	15
Modular Functional Test Sequences for Test Compaction	15
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	15
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	15
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	15
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	14
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	14
NoCFuzzer: Automating NoC Verification in UVM	14
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3D QLC NAND Flash	14
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	14
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	14
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	14
A Compact Gated-Synapse Model for Neuromorphic Circuits	14
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	14
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	14
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	14
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	14
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	14
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	14
Data-Driven Feature Selection Framework for Approximate Circuit Design	14
Varying Periods of In-Field Testing With Storage and Counter Based Logic Built-In Self-Test	14
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	14
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	14
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	13
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	13
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	13
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	13
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	13
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	13
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	13
Multi-Objective Coverage Optimization for 3D Heterogeneous Wireless Sensor Networks	13
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	13
Methodology for Distributed-ROM-Based Implementation of Finite State Machines	13
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	13
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL Assisted Potential Growth in 3 D NAND Flash String	13
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	13
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	13
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	13
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	13
An LDE-Aware g m /I D -Based Hybri	13
Nested Speculative Execution Attacks via Runahead	13
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	12
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic	12
System-on-Chip Information Flow Validation Under Asynchronous Resets	12
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	12
Toward the Predictability of Dynamic Real-Time DNN Inference	12
Digitally Assisted Mixed-Signal Circuit Security	12
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	12
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	12
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	12
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses	12
Quantifying Information Leakage for Security Verification of Compiler Optimizations	12
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing	12
Test Generation for Functionally Possible Subpaths	12
Counteracting Adversarial Attacks in Autonomous Driving	12
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism	12
Table of Contents	12
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	12
INCAME: Interruptible CNN Accelerator for Multirobot Exploration	12
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	12
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	12
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers	12
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations	12
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation	12
Toward Fully Automated Machine Learning for Routability Estimator Development	12
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing	12
Table of contents	12
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	12
Accelerating Real-Valued FFT on CPU-FPGA Platforms	12
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	12
PTPS: Precision-Aware Task Partitioning and Scheduling for SpMV on CPU-FPGA Heterogeneous Platforms	12
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture	11
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	11
Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy	11
AIoTML: A Unified Modeling Language for AIoT-Based Cyber–Physical Systems	11
Table of Contents	11
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology	11
CoGNN: An Algorithm-Hardware Co-Design Approach to Accelerate GNN Inference With Minibatch Sampling	11
Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units	11
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique	11
Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks	11
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration	11
Automated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs	11
LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms	11
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	11
InstantGR: Scalable GPU Parallelization for 3-D Global Routing	11
Low-Cost Shuffling Countermeasures Against Side-Channel Attacks for NTT-Based Post-Quantum Cryptography	11
FlexFL: Heterogeneous Federated Learning via APoZ-Guided Flexible Pruning in Uncertain Scenarios	11
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks	11
Flexible Inverse Design of Microwave Filter Customized on Demand With Wavelet Transform Deep Learning	11
Timing-Aware Qubit Mapping and Gate Scheduling Adapted to Neutral Atom Quantum Computing	11