IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training	101
RowHammer: A Retrospective	100
Approximation Attacks on Strong PUFs	87
Hardware/Software Co-Exploration of Neural Architectures	83
A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors	76
High-Level Synthesis Design Space Exploration: Past, Present, and Future	69
MRIMA: An MRAM-Based In-Memory Accelerator	66
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices	65
Keynote: A Disquisition on Logic Locking	64
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools	62
An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration	59
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars	56
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors	55
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement	55
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults	55
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput	54
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators	54
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	53
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training	46
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets	45
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	44
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems	42
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs	40
QuantHD: A Quantization Framework for Hyperdimensional Computing	40
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start	39

Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective	39
Low Bit-Width Convolutional Neural Network on RRAM	39
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking	38
Advanced Equivalence Checking for Quantum Circuits	38
High Frequency Meminductor Emulator Employing VDTA and its Application	37
A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory	37
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication	36
NPU Thermal Management	35
Exploring Renewable-Adaptive Computation Offloading for Hierarchical QoS Optimization in Fog Computing	34
QuCTS—Single-Flux Quantum Clock Tree Synthesis	33
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search	33
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning	32
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture	32
A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors	31
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper	31
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks	31
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling	30
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks	30
Energy-Efficient Real-Time UAV Object Detection on Embedded Platforms	30
Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation	30
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC	29
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization	29
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture	29
Efficient Federated Learning for Cloud-Based AIoT Applications	29
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems	29
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	29
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble	28
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine	28
A Memristive Spiking Neural Network Circuit With Selective Supervised Attention Algorithm	28
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs	28
AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores	27
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems	27
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures	27
Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips	26
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs	26
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA	26
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network	26
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs	25
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs	25
WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm	25
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	25
Everything Leaves Footprints: Hardware Accelerated Intermittent Deep Inference	25
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan	25
Multilayer Memristive Neural Network Circuit Based on Online Learning for License Plate Detection	24
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA	24
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection	24
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey	24
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System	24
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications	23
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training	23

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars	23
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices	23
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model	22
Exploring Edge Computing for Multitier Industrial Control	22
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems	22
Enabling On-Device CNN Training by Self-Supervised Instance Filtering and Error Map Pruning	21
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging	21
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips	21
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	21
High-Dimensional Uncertainty Quantification of Electronic and Photonic IC With Non-Gaussian Correlated Process Variations	21
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform	21
Modeling and Simulating Electromagnetic Fault Injection	20
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists	20
Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors	20
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks	19
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants	19
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments	19
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding	19
Asymptotically Optimal Circuit Depth for Quantum State Preparation and General Unitary Synthesis	19
Memristor Model Optimization Based on Parameter Extraction From Device Characterization Data	19
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist	19
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips	19
Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm	19
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs	19
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning	18
Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures	18
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis	18
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design	18
UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting	18
High Performance Modular Multiplication for SIDH	18
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems	18
An Automated Topology Synthesis Framework for Analog Integrated Circuits	18
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search	18
Efficient Scheduling of Irregular Network Structures on CNN Accelerators	18
A DVFS-Weakly Dependent Energy-Efficient Scheduling Approach for Deadline-Constrained Parallel Applications on Heterogeneous Systems	17
Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information	17
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System	17
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator	17
Practical Attacks on Deep Neural Networks by Memory Trojaning	17
Improved Mapping of Quantum Circuits to IBM QX Architectures	17
TritonRoute: The Open-Source Detailed Router	17
A Dynamic Look-Ahead Heuristic for the Qubit Mapping Problem of NISQ Computers	17
Fast DRAM PUFs on Commodity Devices	17
Mathematical Modeling Analysis of Strong Physical Unclonable Functions	17
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits	17
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis	17
H₂O-Cloud: A Resource and Quality of Service-Aware Task Scheduling Framework for Warehouse-Scale Data Centers	17
Analog and Mixed-Signal IC Security via Sizing Camouflaging	17
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models	17
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal	17
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash	16
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX	16
Multilabel Deep Learning-Based Side-Channel Attack	16
Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions	16
DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices	16
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm	16
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion	16
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale	16
Logic Synthesis of Approximate Circuits	16
Leakage-Aware Predictive Thermal Management for Multicore Systems Using Echo State Network	16
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect	16
On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment	15
A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects	15
AnyHLS: High-Level Synthesis With Partial Evaluation	15
Semisupervised Hotspot Detection With Self-Paced Multitask Learning	15
ChordMap: Automated Mapping of Streaming Applications Onto CGRA	15
Optrone: Maximizing Performance and Energy Resources of Drone Batteries	15
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture	15
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	15
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime	15
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance	14
LOOPLock: Logic Optimization-Based Cyclic Logic Locking	14
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification	14
Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach	14
Assume–Guarantee Distributed Synthesis	14
Approaches for Assigning Offsets to Signals for Improving Frame Packing in CAN-FD	14
A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture	14
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming	14
BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction	14
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs	14

Test and Yield Loss Reduction of AI and Deep Learning Accelerators	14
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks	14
Hardware Memory Management for Future Mobile Hybrid Memory Systems	14
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm	14
Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance	14
SCANN: Synthesis of Compact and Accurate Neural Networks	14
Defect-Oriented Test: Effectiveness in High Volume Manufacturing	14
Hardware Trojan Detection Using Backside Optical Imaging	14
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection	13
Hardware Trojan Detection using Graph Neural Networks	13
Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems	13
Attack-Aware Detection and Defense to Resist Adversarial Examples	13
C-Testing and Efficient Fault Localization for AI Accelerators	13
Logic Bug Detection and Localization Using Symbolic Quick Error Detection	13
Online Signal Monitoring With Bounded Lag	13
Advanced Functional Decomposition Using Majority and Its Applications	13
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V	13
A Design Framework for Invertible Logic	13
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing	13
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices	13
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach	13
Optimizing Sensor Deployment and Maintenance Costs for Large-Scale Environmental Monitoring	13
From C/C++ Code to High-Performance Dataflow Circuits	13
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs	13
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors	13
Robust Deep Reservoir Computing Through Reliable Memristor With Improved Heat Dissipation Capability	13
Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase-Change Memory Device	13
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling	13
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation	13
Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing	13
Detecting Failures and Attacks via Digital Sensors	13
ABCFI: Fast and Lightweight Fine-Grained Hardware-Assisted Control-Flow Integrity	13
HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs	13
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms	13
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip	12
Toward a High-Performance and Low-Loss Clos–Benes-Based Optical Network-on-Chip Architecture	12
An Edge 3D CNN Accelerator for Low-Power Activity Recognition	12
GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis	12
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability	12
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network	12
Resistorless Memristor Emulators: Floating and Grounded Using OTA and VDBA for High-Frequency Applications	12
BonnCell: Automatic Cell Layout in the 7-nm Era	12
Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory	12
Patch-Based Data Management for Dual-Copy Buffers in RAID-Enabled SSDs	12
ViA: A Novel Vision-Transformer Accelerator Based on FPGA	12
Safety Analysis of Embedded Controllers Under Implementation Platform Timing Uncertainties	12
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations	12
Pin-Accessible Legalization for Mixed-Cell-Height Circuits	12
Reconfigurable and Low-Complexity Accelerator for Convolutional and Generative Networks Over Finite Fields	12
Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs	12
Maximal Independent Fault Set for Gate-Exhaustive Faults	12
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning	12
RANC: Reconfigurable Architecture for Neuromorphic Computing	12
Faster Region-Based Hotspot Detection	12
Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel	12
Security-Aware Obfuscated Priority Assignment for CAN FD Messages in Real-Time Parallel Automotive Applications	12
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	12
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	11
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks	11
Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems	11
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms	11
Development of Programmable Logic Array for Multiple-Valued Logic Functions	11
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network	11
Learning-Based Quality Management for Approximate Communication in Network-on-Chips	11
Improving Reliability of Soft Real-Time Embedded Systems on Integrated CPU and GPU Platforms	11
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection	11
Multitarget Sample Preparation Using MEDA Biochips	11
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations	11
Deterministic Stellar BIST for Automotive ICs	11
Automated Design of Analog Circuits Using Reinforcement Learning	11
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes	11
eWASM: Practical Software Fault Isolation for Reliable Embedded Devices	11
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach	11
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection	11
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips	11
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking	11
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques	11
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power	11
System-Level Energy-Aware Design Methodology Towards End-To-End Response Time Optimization	11
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	11
Power Delivery Exploration Methodology Based on Constrained Optimization	11
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine	11
Swallow: A Versatile Accelerator for Sparse Neural Networks	11
Divide and Slide: Layer-Wise Refinement for Output Range Analysis of Deep Neural Networks	11
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs	11
When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?	11
Detecting Hardware Trojans Using Combined Self-Testing and Imaging	11
Swarm Intelligence-Based Task Scheduling for Enhancing Security for IoT Devices	11
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems	11
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation	11
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs	11
FLASH: Fast, Parallel, and Accurate Simulator for HLS	11
SRAF Insertion via Supervised Dictionary Learning	11
PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization	10
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip	10