IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Table of Contents	156
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	113
Table of Contents	104
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	74
Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System	73
CMCache: An Adaptive Cross-Level Data Placement Method for Multi-Level Cache	65
MACS: A Multi-Domain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators	64
GIRD: A Green IR-Drop Estimation Method	59
GNN-Based Timing Prediction in Pre-Routing Stage With Multi-Task Learning Strategy	58
Study of 3D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM	57
vmPTP: Precise Time Protocol for Inter-VM Communication in Embedded Virtualized Systems	54
Erratum to “Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs” [Jan 21 171-184]	51
Advancing Neuromorphic Architecture Towards Emerging Spiking Neural Network on FPGA	50
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	50
iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree	50
Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDs	49
HaloFL: Efficient Heterogeneity-Aware Federated Learning Through Optimal Submodel Extraction and Dynamic Sparse Adjustment	49
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	47
Practical Attacks on Deep Neural Networks by Memory Trojaning	47
A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips	47
A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems	41
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	39
Counterexample Guided Neural Network Quantization Refinement	39
Coexisting Hyperchaos in a Memristive Neuromorphic Oscillator	37
RoboSpike: Fully Utilizing the Heterogeneous System with Subcallback Scheduling in ROS 2	37

Table of Contents	36
Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach	35
Enabling ILP-Based DSE for Multigranularity, Unified Domain Platforms With DmTSAR-ILP	34
VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis	34
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	33
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	33
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	33
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	32
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness	31
Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks	30
An MIV Test Method Using High-Precision Voltage Dividers	30
A Bridge-Based Compression Algorithm for Topological Quantum Circuits	30
A Study of the Electroforming Process in 1T1R Memory Arrays	30
An Efficient Branch-and-Bound Routing Optimization Method for Optical NoCs	29
Revisiting Assumptions Ordering in CAR-Based Model Checking	29
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files	29
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	28
Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs	27
On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers	27
Table of Contents	27
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	27
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	25
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	25
Table of Contents	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
Table of Contents	24
Table of contents	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
2022 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 41	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	23
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	23
Accurate Multi-segment Probability Density Estimation Through Moment Matching	22
FRL: Fast and Reconfigurable Accelerator for Distributed Sound Source Localization	22
Table of Contents	22
FeFET-Based In-Memory Hyperdimensional Encoding Design	22
LayoutCopilot: An LLM-Powered Multi-Agent Collaborative Framework for Interactive Analog Layout Design	22
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	22
Superscalar Time-Triggered Versatile-Tensor Accelerator	22
MinMaxEntropy: Bound Model Errors for Side-Channel Leakages from Information Theory	21
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	21
RaPC: Raw Bit Error Rate Aware Polar Coding for 3D NAND Flash Memory	21
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units	21
Neural Rendering Acceleration With Deferred Neural Decoding and Voxel-Centric Data Flow	21
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits	21
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	21
Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events	20
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	20
Prism-SSD: A Flexible Storage Interface for SSDs	20

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	20
ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC	19
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	19
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design	19
Exploring the Potential Benefits of Alternative Quantum Computing Architectures	19
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction	19
AntiDoteX: Attention-Based Dynamic Optimization for Neural Network Runtime Efficiency	19
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	19
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	19
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	19
Personalized Neural Network for Patient-Specific Health Monitoring in IoT: A Metalearning Approach	18
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	18
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	18
Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes	18
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	18
Contract-Based Hierarchical Modeling and Traceability of Heterogeneous Requirements	17
Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography	17
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	17
Tidal-Tree-Mem: Toward Read-Intensive Key-Value Stores With Tidal Structure Based on LSM-Tree	17
Securing Approximate Computing Systems via Obfuscating Approximate-Precise Boundary	17
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches	17
Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm	17
Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V	17
Structured Term Pruning for Computational Efficient Neural Networks Inference	17
F-LEMMA: Fast Learning-Based Energy Management for Multi-/Many-Core Processors	17
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning	17
TEA-Z: A Tiny and Efficient Architecture Based on Z Channel for Image Watermarking and Its Versatile Hardware Implementation	17
OPIMA: Optical Processing-in-Memory for Convolutional Neural Network Acceleration	16
EASTER: Learning to Split Transformers at the Edge Robustly	16
CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory	16
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture	16
DREAMx: A Data-Driven Error Estimation Methodology for Adders Composed of Cascaded Approximate Units	16
Learning Memory-Contention Timing Models With Automated Platform Profiling	16
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	16
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	16
An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator	16
HotaQ: Hardware Oriented Token Adaptive Quantization for Large Language Models	16
MII: A Multifaceted Framework for Intermittence-Aware Inference and Scheduling	16
SENTINEL: Securing Indoor Localization Against Adversarial Attacks With Capsule Neural Networks	16
CSA-CiM: Enhancing Multi-Functional Computing-in-Memory With Configurable Sense Amplifiers	15
ML-Based Thermal and Cache Contention Alleviation on Clustered Manycores With 3-D HBM	15
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	15
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model	15
A High-Performance RDMA NIC With Ultra-Highly Scalable Connections	15
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	15
Hyper Parametric Timed CTL	15
Non-invasive Methodology for the Age Estimation of ICs using Gaussian Process Regression	15
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction	15
Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet	15
Horae: A Hybrid I/O Request Scheduling Technique for Near-Data Processing-Based SSD	15
Interval Image Abstraction for Verification of Camera-Based Autonomous Systems	15
Arch2End: Two-Stage Unified System-Level Modeling for Heterogeneous Intelligent Devices	15
COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set	15
iNVMFS: An Efficient File System for NVRAM-Based Intermittent Computing Devices	15
Differentiable Inference of Temporal Logic Formulas	15
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge	14
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs	14
GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks	14
Automated Design for Multi-Organ-on-Chip Geometries	14
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators	14
SR-BIP: A Soft Error-Resilient Binary Neural Network Inference Processor	14
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks	14
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	14
WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs	14
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	14
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	14
Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors	14
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip	14
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	14
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	14
RF Switched-Capacitor Power Amplifier Modeling	14
A Fast Method to Estimate Through-Bump Current for Power Delivery Verification	14
B-HTRecognizer: Bit-Wise Hardware Trojan Localization Using Graph Attention Networks	14
A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization	14
Making Frequent-Pattern Mining Scalable, Efficient, and Compact on Nonvolatile Memories	14
hPRESS: A Hardware-Enhanced Proxy Re-Encryption Scheme Using Secure Enclave	13
Intermittent-Aware Distributed Concurrency Control	13
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults	13
Optimizing AES Threshold Implementation Under the Glitch-Extended Probing Model	13
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers	13

Fast and Scaled Counting-Based Stochastic Computing Divider Design	13
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA	13
Contamination-Aware Synthesis for Programmable Microfluidic Devices	13
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits	13
Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level	13
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	13
Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS	13
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement	13
Netwise Detection of Hardware Trojans Using Scalable Convolution of Graph Embedding Clouds	13
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints	13
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids	13
Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model	13
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs	13
Numerical Insight Into the Origin of Nonreciprocity and Performance Enhancement in Nonreciprocal Bandpass Filters Using Evolutionary Algorithm	13
Instiller: Toward Efficient and Realistic RTL Fuzzing	13
Design of Sequential Load Modulation Balance Amplifier Using Multiobjective Particle Swarm Algorithm	13
A Fast SIE Solver With Cut Set Analysis and Terminals as Supernodes for Interconnects	13
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration	13
ZoneLife: How to Utilize Data Lifetime Semantics to Make SSDs Smarter	13
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs	12
Efficient Block Storage in the Cloud	12
Automatic Mapping of Heterogeneous DNN Models on Adaptive Multiaccelerator Systems	12
Approximate DCT and Quantization Techniques for Energy-Constrained Image Sensors	12
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC	12
MCAM: Memductance Components Adaptive Model for Efficient Modeling of Memductance of Memristive Devices for Neuromorphic Circuits and Systems	12
Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients	12
Multistage Charge Pump Design Methodology for Zero-Crossing-Based Amplifiers	12
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits	12
Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric	12
Optimizing Secure Deletion in Interlaced Magnetic Recording With Move-on-Cover Approach	12
PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search	12
Optimization of High-Efficiency GaN Load Modulated Balanced Amplifier for Integrated Sensing and Communication Applications	12
LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN	12
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN Accelerators	12
iCheck: Progressive Checkpointing for Intermittent Systems	11
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition	11
Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics	11
Efficient Batched Inference in Conditional Neural Networks	11
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	11
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration	11
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning	11
Leveraging Probabilistic Switching in Superparamagnets for Temporal Information Encoding in Neuromorphic Systems	11
Energy-Efficient Spintronic-Based Neuromorphic Computing System Using Current Mode Track and Termination Circuit	11
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort	11
Attack-Aware Detection and Defense to Resist Adversarial Examples	11
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	11
SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm	11
A Point Transformer Accelerator With Distribution-Aware Heuristic Distance Calculation	11
SimDiff: Point Cloud Acceleration by Utilizing Spatial Similarity and Differential Execution	11
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	11
General Purpose Deep Learning Accelerator Based on Bit Interleaving	11
Verification of Camera-Based Autonomous Systems	11
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools	11
GNN-Based Hierarchical Annotation for Analog Circuits	11
pGRASS-Solver: A Graph Spectral Sparsification-Based Parallel Iterative Solver for Large-Scale Power Grid Analysis	11
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	11
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	11
Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs	11
Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis	11
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition	11
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	11
On Input Generators for Cyber–Physical Systems Falsification	11
iPROBE: Internal Shielding Approach for Protecting Against Front-Side and Back-Side Probing Attacks	10
Statistical Modeling of Soft Error Influence on Neural Networks	10
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	10
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming	10
Entropy Reduction Model for Pinpointing Differential Fault Analysis on SIMON and SIMECK Ciphers	10
1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving	10
Code Synthesis for Dataflow-Based Embedded Software Design	10
MSA: A Novel App Development Framework for Transparent Multiscreen Support on Android Apps	10
Analog Building Blocks Optimization for Low-Pass Filter of IEEE 802.11n Wireless LAN: OTA and CCII	10
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	10
PMEH: A Parallel and Write-Optimized Extendible Hashing for Persistent Memory	10
Multiagent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks	10
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures	10
TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks	10
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	10
Enhanced Built-In Self-Diagnosis and Self-Repair Techniques for Daisy-Chain Design in MEDA Digital Microfluidic Biochips	10
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	10
Exploring the Effect of Energy Storage Sizing on Intermittent Computing System Performance	10
Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units	10
Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance	10
Locality-Based Encoder and Model Quantization for Efficient Hyper-Dimensional Computing	10
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks	10
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	10
PDF: Path-Oriented, Derivative-Free Approach for Safety Falsification of Nonlinear and Nondeterministic CPS	10
A Multilabel Active Learning Framework for Microcontroller Performance Screening	10
Bridging Mismatched Granularity Between Embedded File Systems and Flash Memory	10
Automated Design Space Exploration for Optimized Deployment of DNN on Arm Cortex-A CPUs	10
Cooperative Communication Between Two Transiently Powered Sensor Nodes by Reinforcement Learning	10
GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults	9
MFS: A Brain-Inspired Memory Formation System for GAN	9
L2O-ILT: Learning to Optimize Inverse Lithography Techniques	9
A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain Systems	9
H2B: Crypto Hash Functions Based on Hybrid Ring Generators	9