Journal of Electronic Testing-Theory and Applications

Article	Citations
New Editors – 2022	19
Editorial	18
Test Technology Newsletter	15
Test Technology Newsletter	14
A Review of Various Defects in PCB	14
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	13
Editorial	12
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	11
Editorial	11
Editorial	9
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	9
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	7
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	7
2022 Reviewers	7
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	7
A Framework for Configurable Joint-Scan Design-for-Test Architecture	6
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	6
Incomplete Testing of SOC	6
Identifying Resistive Open Defects in Embedded Cells under Variations	5
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	5
Deep Soft Error Propagation Modeling Using Graph Attention Network	5
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	5
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	5
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	5
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs	5

Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	5
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	5
E3C Techniques for Protecting NAND Flash Memories	5
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	4
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	4
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method	4
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	4
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	4
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	4
Design and Verification of a SAR ADC SystemVerilog Real Number Model	4
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	4
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance	4
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	4
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	4
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	4
Editorial	3
Hardware Trojan Free Netlist Identification: A Clustering Approach	3
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	3
Spectrum Analyzer Based on a Dynamic Filter	3
Editorial	3
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	3
Test Technology Newsletter	3
Test Technology Newsletter	3
Test Technology Newsletter	2
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	2
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads	2
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing	2
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	2
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	2
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes	2
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula	2
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	2
Automated Design Error Debugging of Digital VLSI Circuits	2
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	2
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	2
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	2
A Low-cost BIST Design Supporting Offline and Online Tests	2
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	2
Instant Test and Repair for TSVs using Differential Signaling	2
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	2
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits	2
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	2
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application	1
Editorial	1
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	1
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	1
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	1
Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm	1
Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability	1
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs	1

Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	1
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems	1
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network	1
2023 JETTA-TTTC Best Paper Award	1
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms	1
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application	1
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality	1
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	1
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	1
Test Technology Newsletter	1
Performance Efficient and Fault Tolerant Approximate Adder	1
2024 Reviewers	1
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	1
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	1
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	1
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	1
Editorial	1
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations	1
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips	1
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	1
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	1
Design of a Low Noise Amplifier Based on Novel Monolayer Graphene FET	1
Editorial	1
A Survey of PCB Defect Detection Algorithms	1
Editorial	1
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	1
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	0
New Second-order Threshold Implementation of Sm4 Block Cipher	0
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	0
Editorial	0
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm	0
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	0
Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity	0
Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System	0
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	0
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	0
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	0
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	0
Formal Verification of Universal Numbers using Theorem Proving	0
Editorial	0
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	0
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	0
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	0
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	0
Generating Synthetic Layout Test Patterns using Deep Learning	0
Radiation Tolerant SRAM Cell Design in 65nm Technology	0
Reliability Analysis for a GaAs LNA with Temperature Stress	0
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	0
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	0
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	0
A Systematic Bit Selection Method for Robust SRAM PUFs	0
Editorial	0
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	0
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model	0
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	0
An Automatic Software Testing Method to Discover Hard-to-Detect Faults Using Hybrid Olympiad Optimization Algorithm	0
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	0
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	0
2021 Reviewers	0
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	0
Test Technology Newsletter	0
2021 JETTA-TTTC Best Paper Award	0
ADC Dynamic Parameter Testing Scheme Under Relaxed Conditions	0
SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model	0
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications	0
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor	0
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	0
Test Technology Newsletter	0
Effective Software Mutation-Test Using Program Instructions Classification	0
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	0
A New Neural Network Based on CNN for EMIS Identification	0
Journal of Electronic Testing: Theory and Applications New Editors – 2023	0
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	0
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	0
Editorial	0
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	0
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	0
HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits	0
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	0
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	0

The Detection of Malicious Modifications in the FPGA	0
Modeling and Parasitic Extraction of the MM9 Transistor for GHz/THz CMOS RF Circuit Design	0
Editorial	0
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	0
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	0
A New Approximate 4-2 Compressor using Merged Sum and Carry	0
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	0
YOLOv8-TDD: An Optimized YOLOv8 Algorithm for Targeted Defect Detection in Printed Circuit Boards	0
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN	0
A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss	0
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	0
Multiple Retest Systems for Screening High-Quality Chips	0
Test Technology Newsletter	0
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	0
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets	0
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	0
Hardware Obfuscation for IP Protection of DSP Applications	0
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	0
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	0
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	0
Editorial	0
Editorial	0
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm	0
A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques	0
Test Technology Newsletter	0
Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation	0
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram	0
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	0
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	0
A Survey and Recent Advances: Machine Intelligence in Electronic Testing	0
TTTC Newsletter	0
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees	0
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits	0
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	0
Test Technology Newsletter	0
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	0
Editorial	0
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field	0
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	0
A Novel Two-Stage Model Based SCA against secAES	0
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	0
Editorial	0
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	0
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization	0
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	0
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM	0
Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source	0
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks	0
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	0
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	0
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	0
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	0
Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment	0
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost	0
Editorial	0
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	0
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	0
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	0
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models	0
Efficient Selective Image Fusion: A PCB Diagnosis Approach and Implementation	0
2023 JETTA Reviewers	0
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs	0
Stress-Aware Periodic Test of Interconnects	0
2022 JETTA-TTTC Best Paper Award	0
Test Technology Newsletter	0
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	0
Test Technology Newsletter	0
2020 JETTA-TTTC Best Paper Award	0
Editorial	0
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	0
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	0