Journal of Electronic Testing-Theory and Applications

Papers
(The TQCC of Journal of Electronic Testing-Theory and Applications is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function39
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission19
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm16
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits13
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach13
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis13
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems12
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network12
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing12
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems12
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm10
A New Approximate 4-2 Compressor using Merged Sum and Carry9
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach9
Performance Efficient and Fault Tolerant Approximate Adder8
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network8
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security8
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations8
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era8
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest7
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society7
A Program-Output Estimator for Software Testing Using Program Analysis and Deep Learning Algorithms7
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision7
Enhanced Moth Flame Optimization Algorithm Entropy-Based Centroid SVM-Based Software Defect Prediction7
Editorial6
Editorial6
SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method6
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey5
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model5
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation5
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries5
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network5
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits5
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems5
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization5
Editorial5
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach4
2021 Reviewers4
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram4
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors4
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift4
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction4
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism4
2021 JETTA-TTTC Best Paper Award4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach4
2022 Reviewers4
Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source3
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment3
Instant Test and Repair for TSVs using Differential Signaling3
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs3
Deep Soft Error Propagation Modeling Using Graph Attention Network3
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications3
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs3
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements3
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM3
Test Technology Newsletter3
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis3
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