Journal of Electronic Testing-Theory and Applications

Papers
(The TQCC of Journal of Electronic Testing-Theory and Applications is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)
ArticleCitations
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm29
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function16
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission15
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis12
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach12
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement11
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems11
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network10
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations10
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems9
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision8
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm8
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits8
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security7
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network7
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach7
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing7
Performance Efficient and Fault Tolerant Approximate Adder7
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era7
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey6
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest6
A New Approximate 4-2 Compressor using Merged Sum and Carry6
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations6
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network5
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society5
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation5
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis5
Editorial5
SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method5
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits5
Editorial5
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization4
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach4
2021 Reviewers4
Editorial4
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries4
2020 JETTA-TTTC Best Paper Award4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors4
2021 JETTA-TTTC Best Paper Award4
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach3
Deep Soft Error Propagation Modeling Using Graph Attention Network3
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements3
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram3
2022 Reviewers3
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications3
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift3
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction3
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism3
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends3
New Second-order Threshold Implementation of Sm4 Block Cipher2
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR2
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security2
Instant Test and Repair for TSVs using Differential Signaling2
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs2
Automated Design Error Debugging of Digital VLSI Circuits2
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation2
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing2
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles2
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process2
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs2
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM2
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis2
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution2
Test Technology Newsletter2
Hardware Obfuscation for IP Protection of DSP Applications2
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP2
Test Technology Newsletter2
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment2
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm2
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