OOIR: Observatory of International Research

Papers

(The TQCC of Journal of Electronic Testing-Theory and Applications is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)

Article	Citations
New Editors – 2022	19
Editorial	18
Test Technology Newsletter	15
Test Technology Newsletter	14
A Review of Various Defects in PCB	14
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	13
Editorial	12
Editorial	11
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	11
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	9
Editorial	9
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	7
2022 Reviewers	7
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	7
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	7
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	6
Incomplete Testing of SOC	6
A Framework for Configurable Joint-Scan Design-for-Test Architecture	6
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	5
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	5
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	5
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs	5
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	5
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	5
E3C Techniques for Protecting NAND Flash Memories	5

Identifying Resistive Open Defects in Embedded Cells under Variations	5
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	5
Deep Soft Error Propagation Modeling Using Graph Attention Network	5
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method	4
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	4
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	4
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	4
Design and Verification of a SAR ADC SystemVerilog Real Number Model	4
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	4
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance	4
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	4
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	4
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	4
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	4
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	4
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	3
Spectrum Analyzer Based on a Dynamic Filter	3
Editorial	3
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	3
Test Technology Newsletter	3
Test Technology Newsletter	3
Editorial	3
Hardware Trojan Free Netlist Identification: A Clustering Approach	3
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	2
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes	2
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula	2
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	2
Automated Design Error Debugging of Digital VLSI Circuits	2
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	2
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	2
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	2
A Low-cost BIST Design Supporting Offline and Online Tests	2
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	2
Instant Test and Repair for TSVs using Differential Signaling	2
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	2
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits	2
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	2
Test Technology Newsletter	2
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	2
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads	2
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing	2
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	2