OOIR: Observatory of International Research

Papers

(The TQCC of Journal of Electronic Testing-Theory and Applications is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	23
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	20
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	16
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	15
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	15
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	15
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	12
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	12
Spectrum Analyzer Based on a Dynamic Filter	11
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	10
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	10
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	10
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	9
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network	8
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	8
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	8
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	7
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security	7
Performance Efficient and Fault Tolerant Approximate Adder	6
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	6
A New Approximate 4-2 Compressor using Merged Sum and Carry	6
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	6
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	6
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach	6
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	6

Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System	5
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	5
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	5
Test Technology Newsletter	5
Editorial	5
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	5
Editorial	4
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	4
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	4
Editorial	4
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	4
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	4
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	4
2021 Reviewers	3
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram	3
Deep Soft Error Propagation Modeling Using Graph Attention Network	3
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	3
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	3
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	3
2020 JETTA-TTTC Best Paper Award	3
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	3
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	3
2021 JETTA-TTTC Best Paper Award	3
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	3
2022 Reviewers	3
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	3
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	2
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	2
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	2
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	2
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	2
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	2
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	2
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment	2
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	2
New Second-order Threshold Implementation of Sm4 Block Cipher	2
Test Technology Newsletter	2
Instant Test and Repair for TSVs using Differential Signaling	2
Test Technology Newsletter	2
Automated Design Error Debugging of Digital VLSI Circuits	2
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	2
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	2
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	2