OOIR: Observatory of International Research

Papers

(The TQCC of Journal of Electronic Testing-Theory and Applications is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing	22
Spectrum Analyzer Based on a Dynamic Filter	13
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices	12
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums	11
Hardware Obfuscation for IP Protection of DSP Applications	9
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	9
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	8
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	8
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	8
A Review of Various Defects in PCB	7
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults	7
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	7
An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic	6
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier	6
Model Transferability from ImageNet to Lithography Hotspot Detection	6
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model	6
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review	6
Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm	6
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	6
Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles	5
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	5
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	5
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	4
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	4

Automated Design Error Debugging of Digital VLSI Circuits	4
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	4
Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods	4
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	4
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	4
Hardware Trojan Free Netlist Identification: A Clustering Approach	4
A Fault Verification Method Based on the Substitution Theorem and Voltage-Current Phase Relationship	4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
A Systematic Bit Selection Method for Robust SRAM PUFs	4
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	4
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	4
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	4
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	3
Tipping Point Analysis of Electrical Resistance Data with Early Warning Signals of Failure for Predictive Maintenance	3
Part I: Evaluation for Hardware Trojan Detection Based on Electromagnetic Radiation	3
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	3
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	3
Single Particle Fault Injection Signal Generation Method Using Gaussian Cloud Model	3
Novel MEMS Piezoresistive Sensor with Hair-Pin Structure to Enhance Tensile and Compressive Sensitivity and Correct Non-Linearity	3
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	3
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	3
Identifying Resistive Open Defects in Embedded Cells under Variations	3
Multiple Retest Systems for Screening High-Quality Chips	2
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	2
Estimating Operational Age of an Integrated Circuit	2
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	2
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	2
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	2
Diagnosis of Incipient Faults in Nonlinear Analog Circuits Based on High Order Moment Fractional Transform	2
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	2
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	2
A New Neural Network Based on CNN for EMIS Identification	2
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables	2
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	2
Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip	2
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	2
Deep Soft Error Propagation Modeling Using Graph Attention Network	2
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	2
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	2
A probability density estimation algorithm on multiwavelet for the high-resolution ADC	2
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	2
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit	2
TRAP-GATE: A Probabilistic Approach to Enhance Hardware Trojan Detection and its Game Theoretic Analysis	2
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	2
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	2