OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 28. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-12-01 to 2025-12-01.)

Article	Citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	60
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	60
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	60
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	58
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	51
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	48
Table of Contents	46
Hidden Costs of Analog Deobfuscation Attacks	45
Behavioral Model for High-Speed SAR ADCs With On-Chip References	45
Diagnostic Test Point Insertion and Test Compaction	42
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	42
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	41
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	41
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	41
Analysis and Design of Magnetically Tuned W -Band Oscillators	39
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	39
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	36
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	35
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	35
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	35
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication	34
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	33
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	33
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	32
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters	31

Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	31
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	30
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	29
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	28