OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 24. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
Architecture of Cobweb-Based Redundant TSV for Clustered Faults	131
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell	71
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs	68
Cryptographic Accelerators for Digital Signature Based on Ed25519	61
Mixed-Signal Computing for Deep Neural Network Inference	50
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks	50
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing	45
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse	36
ASSURE: RTL Locking Against an Untrusted Foundry	35
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks	35
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators	35
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions	35
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices	33
PUF-Based Secure Chaotic Random Number Generator Design Methodology	33
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND	30
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers	29
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands	28
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking	28
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator	28
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register	27
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates	26
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions	26
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory	25
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs	24
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling	24

GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures