OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 26. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	57
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	54
Behavioral Model for High-Speed SAR ADCs With On-Chip References	53
Hidden Costs of Analog Deobfuscation Attacks	51
Diagnostic Test Point Insertion and Test Compaction	50
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	42
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	42
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	42
Table of Contents	41
Analysis and Design of Magnetically Tuned W -Band Oscillators	39
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	39
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	39
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	38
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	37
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	37
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	35
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	33
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	33
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	32
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	32
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	31
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	30
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	28
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	27
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	27

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	27
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	26