OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 27. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	105
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	52
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	49
Behavioral Model for High-Speed SAR ADCs With On-Chip References	48
Hidden Costs of Analog Deobfuscation Attacks	45
Diagnostic Test Point Insertion and Test Compaction	45
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	43
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	41
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	38
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	38
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	38
Table of Contents	38
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	37
Analysis and Design of Magnetically Tuned W -Band Oscillators	37
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	35
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	35
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	34
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	33
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	32
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	31
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance	31
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	30
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	30
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	30
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	28

HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	28
Table of Contents	27
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	27