IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	65
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	62
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	62
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	61
A Trifilar Transformer-Based Class-F23 VCO With Noise-Circulating Technology	54
Table of Contents	50
Behavioral Model for High-Speed SAR ADCs With On-Chip References	48
Hidden Costs of Analog Deobfuscation Attacks	48
Diagnostic Test Point Insertion and Test Compaction	45
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	44
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	43
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	42
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	42
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters	41
Analysis and Design of Magnetically Tuned W -Band Oscillators	39
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	39
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	38
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	36
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication	35
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	35
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	35
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	33
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	33
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	33
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	32

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	31
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	30
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	29
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	28
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	27
Table of Contents	26
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	26
Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging	26
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	26
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	26
Editorial New Beginnings for IEEE TVLSI	25
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes	25
IEEE Women in Engineering	25
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	25
Upscale Layer Acceleration on Existing AI Hardware	25
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory	24
A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector	23
Test Methodology for Defect-Based Bridge Faults	23
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique	22
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key	22
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application	22
Test Sequences for Faults in the Scan Logic	22
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era	22
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology	22
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition	21
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	21
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption	21
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	21
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	21
Test Data Compression for Transparent-Scan Sequences	20
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	20
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices	20
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing	20
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application	19
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays	19
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation	19
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W	19
A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5–2.5 GHz in 65-nm CMOS	19
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support	19
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection	19
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications	19
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning	19
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS	18
A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments	18
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory	18
An Ultralow-Energy Voltage Level Shifter With an Output-Cycle-Based Dynamic Biasing Scheme in a 130-nm CMOS Technology	18
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack	18
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators	18
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment	18
A Reconfigurable Multiple Transform Selection Architecture for VVC	17

A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation	17
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing	17
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	17
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array	17
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding	17
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform	17
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	17
An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints	17
CINELL: An Energy-Efficient Compute-In/Near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models	16
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer	16
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD	16
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering	16
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process	16
Test Primitives: The Unified Notation for Characterizing March Test Sequences	16
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer	16
A 0.97 nJ/Conversion BJT-Based Temperature Sensor With a Low-Power Two-Stage Dynamic Comparator	16
Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems	16
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation	16
A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based Distortion Contribution Analysis Tool	16
Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications	15
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	15
Toward Reliable Onboard AI in Space: A Fault-Tolerant Soft GPU-Based System-on-Chip	15
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF	15
An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems	15
A 9T SRAM Computation-in-Memory Architecture With High-Precision MAC, Enhanced Bitline Voltage Margin, and Improved Frequency Performance Over Conventional Architectures	15
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory	15
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs	15
A Fully Integrated Storage-Free Energy Harvesting System With Voltage Self-Regulation and Dual-Channel Power Extraction	15
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m )	15
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices	15
FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling	14
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution	14
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs	14
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs	14
Efficient and Predictable Context Switching for Mixed-Criticality and Real-Time Systems	14
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks	14
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing	14
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction	14
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads	14
An Energy-Efficient Neuromorphic Self-Attention Core Exploiting Dual Sparsity in Neurons and Spikes	13
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs	13
MoE-Sched: Enabling Efficient FPGA Deployment of Mixture-of-Experts Vision Transformers via Coordinated Scheduling	13
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access	13
An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores	13
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform	13
Design and Analysis of the Leapfrog Control-Bounded A/D Converter	13
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces	12
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification	12
Analog Probe Module (APM) for Enhanced IC Observability: From Concept to Application	12
Table of Contents	12
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC	12
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
Impact of Radix-10 Redundant Digit Set [−6, 9] on Basic Decimal Arithmetic Operations	12
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method	11
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices	11
An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling	11
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters	11
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit	11
Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow	11
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme	11
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors	11
Low-Noise Distributed RC Oscillator	11
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip	11
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits	11
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm	11
ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor	11
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection	11
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture	11
Editorial Rolling Out the IEEE TVLSI EDICS	11
A 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS	11
Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array	11
Modular RTIC: Lightweight Real Time for Customized Architectures	11
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection	11
An Energy-Efficient Kalman Filter Coprocessor Design for Multiple-Object Tracking Targeting at Video Understanding	11
Analog Matrix Inversion Circuit Design for Solving Tridiagonal Linear Systems: A Compact and Decoupled Approach	11
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver	11
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10

Table of Contents	10
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks	10
A Low-Ripple DIDO DC–DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH	10
Table of Contents	10
Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC	10
A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time	10
Table of Contents	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network	10
A 12-bit, 1.1-GS/s, Low-Power Flash ADC	10
An 197-μJ/Frame Single-Frame Bundle Adjustment Hardware Accelerator for Mobile Visual Odometry	10
A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme	10
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks	10
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead	10
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10
A Fourth-Order Tunable Bandwidth Gm -C Filter for ECG Detection Achieving −7.9 dBV IIP3 Under a 0.5 V Supply	10
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10
A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection	10
Corrections to “An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation” [Apr 21 667-676]	10
Multiphase Digital Low-Dropout Regulators	10
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients	9
A 380-μW Electrochemical Impedance Measurement System for Protein Sensing	9
PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing	9
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies	9
A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications	9
Posit Process Element for Using in Energy-Efficient DNN Accelerators	9
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design	9
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree	9
General Compilation and Mixed-Precision Partitioning: A Combined Approach for Adaptive On-Device Learning	9
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	9
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests	9
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel	9
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology	9
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention	9
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation	9
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths	9
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers	9
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems	9
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	9
QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations	9
RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference	9
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications	9
Testability Evaluation for Local Design Modifications	9
An Efficient High-Throughput Structured-Light Depth Engine	9
An Area-Energy-Efficient 64–2048 Point FFT With Approximate Plane-Fitting Complex Multipliers	9
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques	9
X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems	9
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM	9
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic	9
A 40-nm Embedded Flash With Highly Reliable Bitline Transmission and Low-Voltage Current Sense Amplifier	9
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors	9
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS	9
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction	9
A Soft Iterative Receiver With Simplified EP Detection for Coded MIMO Systems	9
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	9
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory	8
Stochastic Computing Using Amplitude and Frequency Encoding	8
A High-Order High-Throughput Multibank FFT Engine With Optimized Floating-Point Radix-2 Butterfly Units	8
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing	8
A Mixed-Mode Acceleration via Sparsity-Adjustable Pruning for Balancing Computation Density in Lightweight CNNs	8
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	8
Increase Your Knowledge of Technical Standards	8
Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines	8
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests	8
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array	8
Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic Computing	8
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption	8
A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links	8
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic	8
A 35.2-kHz, 75.4-dB Bulk-Driven OTA Using Degenerative Current Tram Structure	8
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs	8
A High-Throughput Hardware Design for the AV1 Decoder Intraprediction	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	8
RA-Aware Fail Data Collection Architecture for Cost Reduction	8
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL	8
S 3A-NPU: A High-Performance Hardware Accelerator for Spiking Self-Supervised Learning With Dynamic Adaptive Memory Optimization	8
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier	8
12-bit SAR ADC Employing a 9-bit CDAC in Vanilla CMOS 40-nm Technology	8
Physical Attack Protection Techniques for IC Chip Level Hardware Security	8
Addressing Resiliency of In-Memory Floating Point Computation	8
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems	8
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs	8
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations	8
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation	8
Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension	8
Energy-Efficient Encoding for High-Speed Serial Interfaces	8
A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS	8
A Universal Sequential Authentication Scheme for TAPC-Based Test Standards	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	8
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits	8
12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability	8