IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	57
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	54
Behavioral Model for High-Speed SAR ADCs With On-Chip References	53
Hidden Costs of Analog Deobfuscation Attacks	51
Diagnostic Test Point Insertion and Test Compaction	50
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	42
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	42
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	42
Table of Contents	41
Analysis and Design of Magnetically Tuned W -Band Oscillators	39
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	39
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	39
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	38
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	37
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	37
A Trifilar Transformer-Based Class-F23 VCO With Noise-Circulating Technology	35
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	33
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	33
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	32
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	32
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	31
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	30
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	28
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	27
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	27

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	27
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	26
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	25
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	25
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	25
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	24
Table of Contents	24
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	24
Test Data Compression for Transparent-Scan Sequences	23
IEEE Women in Engineering	23
Editorial New Beginnings for IEEE TVLSI	23
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology	22
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing	22
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key	22
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	22
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection	22
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices	21
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era	21
Test Methodology for Defect-Based Bridge Faults	21
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	21
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application	20
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory	20
Upscale Layer Acceleration on Existing AI Hardware	20
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI	20
A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector	20
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	20
Test Sequences for Faults in the Scan Logic	20
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W	20
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique	20
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications	19
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes	19
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption	19
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition	18
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays	18
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering	17
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application	17
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation	17
A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based Distortion Contribution Analysis Tool	17
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support	17
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS	16
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing	16
An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints	16
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory	16
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation	16
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	16
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators	16
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security	15
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment	15
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array	15
Test Primitives: The Unified Notation for Characterizing March Test Sequences	15

Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems	15
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer	15
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform	15
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process	15
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning	15
A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments	15
A Reconfigurable Multiple Transform Selection Architecture for VVC	15
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation	15
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD	15
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack	15
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer	15
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding	15
Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications	14
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads	14
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m )	14
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	14
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	14
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing	14
A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5–2.5 GHz in 65-nm CMOS	14
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs	14
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs	14
A 0.97 nJ/Conversion BJT-Based Temperature Sensor With a Low-Power Two-Stage Dynamic Comparator	14
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction	13
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution	13
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory	13
FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling	13
Toward Reliable Onboard AI in Space: A Fault-Tolerant Soft GPU-Based System-on-Chip	13
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF	13
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform	13
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs	13
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs	13
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access	13
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	13
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs	13
Design and Analysis of the Leapfrog Control-Bounded A/D Converter	13
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks	13
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices	13
Editorial Rolling Out the IEEE TVLSI EDICS	13
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC	12
Multiphase Digital Low-Dropout Regulators	12
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification	12
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method	12
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation	12
Analog Probe Module (APM) for Enhanced IC Observability: From Concept to Application	12
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection	12
Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array	12
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme	12
Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow	12
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces	12
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration	12
Impact of Radix-10 Redundant Digit Set [−6, 9] on Basic Decimal Arithmetic Operations	12
Table of Contents	12
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors	11
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing	11
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit	11
A 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS	11
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications	11
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver	11
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters	11
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip	11
An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling	11
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices	11
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits	11
Low-Noise Distributed RC Oscillator	11
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm	11
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection	11
Modular RTIC: Lightweight Real Time for Customized Architectures	10
Blank page	10
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network	10
A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture	10
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	10
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM	10
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors	10
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks	10
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic	10
Table of contents	10

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	10
Table of Contents	10
Corrections to “An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation” [Apr 21 667-676]	10
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead	10
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel	10
ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor	10
QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations	9
Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC	9
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	9
A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme	9
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths	9
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS	9
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design	9
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks	9
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline	9
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers	9
A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	9
A 380-μW Electrochemical Impedance Measurement System for Protein Sensing	9
An Area-Energy-Efficient 64–2048 Point FFT With Approximate Plane-Fitting Complex Multipliers	9
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	9
A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection	9
Posit Process Element for Using in Energy-Efficient DNN Accelerators	9
PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing	9
Table of Contents	9
Table of Contents	9
A Fourth-Order Tunable Bandwidth Gm -C Filter for ECG Detection Achieving −7.9 dBV IIP3 Under a 0.5 V Supply	9
A 12-bit, 1.1-GS/s, Low-Power Flash ADC	9
An 197-μJ/Frame Single-Frame Bundle Adjustment Hardware Accelerator for Mobile Visual Odometry	9
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems	9
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies	9
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree	9
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention	9
X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems	9
A Low-Ripple DIDO DC–DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH	9
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory	8
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing	8
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption	8
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations	8
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	8
Physical Attack Protection Techniques for IC Chip Level Hardware Security	8
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs	8
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems	8
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests	8
A Soft Iterative Receiver With Simplified EP Detection for Coded MIMO Systems	8
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	8
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits	8
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction	8
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology	8
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic	8
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications	8
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation	8
Testability Evaluation for Local Design Modifications	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	8
An Efficient High-Throughput Structured-Light Depth Engine	8
A High-Throughput Hardware Design for the AV1 Decoder Intraprediction	8
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques	8
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems	8
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs	8
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	8
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	8
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application	7
Table of Contents	7
Stochastic Computing Using Amplitude and Frequency Encoding	7
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V DD Assist and Bitline Leakage Compensation	7
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL	7
Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic Computing	7
A Wideband Input Buffer Based on Cascade Complementary Source Follower	7
12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability	7
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array	7
Increase Your Knowledge of Technical Standards	7
S 3A-NPU: A High-Performance Hardware Accelerator for Spiking Self-Supervised Learning With Dynamic Adaptive Memory Optimization	7
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests	7
Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines	7
A 28-GHz 2-by-2 MIMO Transceiver Deploying Transformer Gain Equalization Technique for 5G New Radio	7
A Robust Integrated Power Delivery Methodology for 3-D ICs	7
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors	7
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments	7
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding	7
Addressing Resiliency of In-Memory Floating Point Computation	7
RA-Aware Fail Data Collection Architecture for Cost Reduction	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator	7
IEEE Computer Society Information	7
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications	7
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks	7
Synthesis of Approximate Parallel-Prefix Adders	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
Functionally Possible Path Delay Faults With High Functional Switching Activity	7
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links	7