OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 5. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	99
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	68
M²-ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization	46
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	46
Hardware–Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA	42
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform	41
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC	41
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM	39
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	37
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications	36
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators	36
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime	35
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars	34
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features	33
All-Rounder: A Flexible AI Accelerator With Diverse Data Format Support and Morphable Structure for Multi-DNN Processing	33
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems	33
High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC	33
TechRxiv: Share Your Preprint Research with the World!	32
A 1 mW–10 W, Over 86.4% Efficiency Tri-Mode Buck Converter With Ripple-Based Control for Mobile Applications	32
Table of contents	31
RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor	30
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	30
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology	30
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	29
Table of Contents	29

A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer	28
FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing	28
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads	28
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	27
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	27
Table of Contents	27
Table of Contents	25
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning	25
Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators	24
A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors	24
A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors	24
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing	24
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	23
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	23
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS	23
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test	23
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	22
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	22
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	22
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	22
Table of contents	22
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	20
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet	19
Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter	19
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	19
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	19
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store	19
Analysis and Design of Magnetically Tuned W -Band Oscillators	19
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	19
Table of Contents	19
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER	19
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	18
Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC	18
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	18
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	18
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation	18
Table of Contents	17
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic	17
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs	17
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application	17
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems	17
VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder	17
Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing	17
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits	17
A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process	17
An Efficient Hard-Detection GRAND Decoder for Systematic Linear Block Codes	17
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation	16
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	16
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data–Index Decoupling Workflow	16
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT	16

Hidden Costs of Analog Deobfuscation Attacks	15
Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge	15
Corrections to “Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator” [Jul 23 1078-1082]	15
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults	15
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter	15
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation	15
A 5-mm², 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems	14
Behavioral Model for High-Speed SAR ADCs With On-Chip References	14
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction	14
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro	14
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	14
Hard-to-Detect Fault Analysis in FinFET SRAMs	13
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System	13
Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing	13
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments	13
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs	13
A 12.93–16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection	13
Physical Attack Protection Techniques for IC Chip Level Hardware Security	13
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM	13
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks	13
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation	13
Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2^m)	12
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming	12
Another Look at Side-Channel-Resistant Encoding Schemes	12
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	12
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel	12
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	12
Testability Evaluation for Local Design Modifications	12
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs	12
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor	12
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic	12
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs	12
Rowhammer Vulnerability of DRAMs in 3-D Integration	12
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs	12
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs	12
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM	12
A 24–40-GHz Broadband Beamforming TRX Front-End IC With Unified Phase and Gain Control for Multiband Phased Array Systems	12
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	11
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation	11
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine	11
A Single-Chip Solution for Diagnosing Peripheral Arterial Disease	11
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches	11
Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs	11
Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System	11
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning	11
Training Accelerator for Two Means Decision Tree	11
Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange	11
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices	11
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance	11
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators	11
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients	11
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications	11
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications	11
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	10
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	10
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS	10
Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks	10
55–100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS	10
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks	10
FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores	10
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	10
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers	10
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures	10
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption	10
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator	10
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications	10
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques	10
Online Fault Detection in ReRAM-Based Computing Systems for Inferencing	10
Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture	10
Detection of Recycled ICs Using Backscattering Side-Channel Analysis	10
Diagnostic Test Point Insertion and Test Compaction	10
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	10
A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain	10
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests	10
CEVGMM: Computationally Efficient Versatile Generic Memristor Model	9
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology	9
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation	9
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory	9
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	9
An Efficient High-Throughput Structured-Light Depth Engine	9

Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V	9
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	9
Table of Contents	9
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023	9
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems	9
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory	9
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process	9
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations	9
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	8
X-Former: In-Memory Acceleration of Transformers	8
A 0.3-V 8.5-μ a Bulk-Driven OTA	8
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact	8
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity	8
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications	8
DRC Violation Prediction After Global Route Through Convolutional Neural Network	8
AxPPA: Approximate Parallel Prefix Adders	8
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator	8
FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization	8
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	8
Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults	8
Retry-Based Synchronization for Online Testing of Identical Logic Blocks	8
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	8
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory	8
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	8
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers	8
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation	8
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	8
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	8
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations	8
Graceful Degradation of Reconfigurable Scan Networks	8
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses	8
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
Table of Contents	7
A 1-MS/s 64-Channel Data Acquisition System With Full-Scale Input Range for Area-Sensitive Application Achieved 165.3-dB FoM_S/Ch	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
Connect. Support. Inspire.	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	7
Table of Contents	7
On Using nMOS–pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier	7
Table of Contents	7
Table of contents	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	7
Increase Your Knowledge of Technical Standards	7
Table of Contents	7
Table of Contents	7
IEEE Women in Engineering	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
Table of Contents	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning	6
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders	6
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC	6
Addressing Resiliency of In-Memory Floating Point Computation	6
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis	6
A 22-nm 264-GOPS/mm² 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs	6
A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules	6
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing	6
A Robust Integrated Power Delivery Methodology for 3-D ICs	6
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition	6
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing	6
A 6–18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS	6
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption	6
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range	6
A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN)	6
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	6
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques	6
Functionally Possible Path Delay Faults With High Functional Switching Activity	6
Test Methodology for Defect-Based Bridge Faults	6
Stochastic Computing Using Amplitude and Frequency Encoding	6
Energy-Efficient Encoding for High-Speed Serial Interfaces	6
Test Sequences for Faults in the Scan Logic	6
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications	6
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era	6
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability	6
Designing Precharge-Free Energy-Efficient Content-Addressable Memories	6
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm² FoM for RF-Based Hybrid Energy Harvesting	6
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories	6
Input-Latency Free Versatile Bit-Serial GF(2^m) Polynomial Basis Multiplication	6
Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects	6
Area Efficient 0.009-mm² 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator	6
Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes	6
Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization	6
ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling	6
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs	6
ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses	6
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks	6