ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition	109
Reduced On-chip Storage of Seeds for Built-in Test Generation	101
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	58
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	33
Graph Neural Networks for High-Level Synthesis Design Space Exploration	27
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	27
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	26
Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation	25
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	24
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation	21
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	18
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	18
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	17
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	17
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning	17
DTGx2: Dual Target Diagnostic Test Generation	14
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	14
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	14
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	13
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis	13
Introduction to the Special Issue on Embedded System Software/Tools	13
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks	12
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	12
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	12
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	12

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	11
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	11
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	11
Component Fault Diagnosability of Hierarchical Cubic Networks	11
Context-aware Data Augmentation for Hardware Code Fault localization	10
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models	10
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	10
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability	10
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	9
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	9
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	9
VeriGen: A Large Language Model for Verilog Code Generation	9
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs	9
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	9
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	8
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	8
RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions	8
Programmable In-memory Computing Circuit of Fast Hartley Transform	8
ParTBC: Faster Estimation of Top- k Betweenness Centrality Vertices on GPU	8
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	8
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	7
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	7
Training PPA Models for Embedded Memories on a Low-data Diet	7
MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures	7
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	7
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems	7
LLM-assisted Bug Identification and Correction for Verilog HDL	7
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	7
Poor Man’s Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach	7
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	7
Detecting Adversarial Examples Utilizing Pixel Value Diversity	7
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	7
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	6
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning	6
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	6
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	6
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	6
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	6
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	6
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey	6
FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI	6
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	6
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	6
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	6
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	6
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	6
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	6
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction	6

Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	6
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	5
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	5
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	5
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	5
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	5
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	5
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	5
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA	5
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	5
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	5
Scan Chain Watermarking : A Graph Neural Network based approach	5
Polling-Based Memory Interface	5
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	5
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices	4
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	4
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization	4
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains	4
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs	4
High-level Synthesis Directives Design Optimization via Large Language Model	4
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	4
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	4
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	4
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling	4
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices	4
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	4
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference	4
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	4
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	4
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0	4
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	4
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	3
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking	3
Synthesis of Clock Networks with a Mode-Reconfigurable Topology	3
Efficient Test Chip Design via Smart Computation	3
Energy-aware Scheduling of Workflow Applications Towards Schedule Length Optimization in Heterogeneous Distributed Embedded Systems	3
Rescuing ReRAM-based Neural Computing Systems from Device Variation	3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips	3
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	3
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm	3
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework	3
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators	3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication	3
Introduction to the Special Issue on Machine Learning for CAD/EDA	3
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together	3
An Improved MCTS Algorithm for Ordered Escape Routing of Differential Pair	3
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences	3
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	3
Structured Dynamic Precision for Deep Neural Networks Quantization	3
ARM-CO-UP: ARM COoperative Utilization of Processors	2
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference	2
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction	2
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	2
Distance-aware Approximate Nanophotonic Interconnect	2
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	2
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface	2
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement	2
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device	2
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System	2
Introduction to the Special Section on Energy-Efficient AI Chips	2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	2
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	2
An Adaptive Application Framework with Customizable Quality Metrics	2
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach	2
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism	2
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies	2
AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing	2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources	2
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips	2
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation	2

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers	2
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits	2
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development	2
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware	2
Unveiling Cross-checking Opportunities in Verilog Compilers	2
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation	2
Sherlock: A Multi-Objective Design Space Exploration Framework	2
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits	2
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming	2
CuPBoP: Making CUDA a Portable Language	2
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference	2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	2
LOGIC: Logic Synthesis for Digital In-Memory Computing	2
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization	2
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning	2
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	2
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	2
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	2
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks	2
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack	2
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing	2
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models	2
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	2
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations	2
Towards Floating Point-Based AI Acceleration: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications	2
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling	1
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing	1
Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics	1
CRM_BF:A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms	1
Pareto Optimization of Analog Circuits Using Reinforcement Learning	1
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits	1
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization	1
Routability-driven Power/Ground Network Optimization Based on Machine Learning	1
A data-centric chip design agent framework for Verilog code generation	1
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization	1
Design Automation Algorithms for the NP-Separate VLSI Design Methodology	1
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture	1
Test-Fleet Scheduling in Complex Validation and Production Environments	1
Mitigating Mode-switch through Run-time Computation of Response Time	1
An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model	1
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC	1
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses	1
Test Point Insertion for Multi-Cycle Power-On Self-Test	1
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder	1
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems	1
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis	1
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning	1
Sorting it out in Hardware: A State-of-the-Art Survey	1
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity	1
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	1
Introduction to the Special Issue on Approximate Systems	1
iPO: Constant Liar Parameter Optimization for Placement with Representation and Transfer Learning	1
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis	1
Flip : Data-centric Edge CGRA Accelerator	1
A Module-Level Configuration Methodology for Programmable Camouflaged Logic	1
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning	1
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs	1
A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values	1
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement	1
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	1
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis	1
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization	1
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan	1
Toward a Human-Readable State Machine Extraction	1
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation	1
Automatic Test Pattern Generation for Robust Quantum Circuit Testing	1
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	1
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories	1
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking	1
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM	1
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors	1
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices	1
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline	1
Global Interconnect Optimization	1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts	1
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect	1
HDLdebugger: Streamlining HDL debugging with Large Language Models	1
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation	1
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators	1
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization	1
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification	1
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis	1
Global Placement Exploiting Soft 2D Regularity	1
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs	1