ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition	138
Reduced On-chip Storage of Seeds for Built-in Test Generation	115
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	61
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	36
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation	33
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	33
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	27
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	27
Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation	27
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	23
Graph Neural Networks for High-Level Synthesis Design Space Exploration	22
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	20
InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems	20
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning	19
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	19
DTGx2: Dual Target Diagnostic Test Generation	18
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	18
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	18
Introduction to the Special Issue on Embedded System Software/Tools	17
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	16
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks	15
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis	15
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	15
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	14
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	14

Scheduling Task Graph Applications on Preloaded Shared-Bus based Heterogeneous Platforms	13
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	13
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models	12
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	12
Component Fault Diagnosability of Hierarchical Cubic Networks	12
Context-aware Data Augmentation for Hardware Code Fault localization	12
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	12
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability	11
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	11
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	11
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	10
VeriGen: A Large Language Model for Verilog Code Generation	10
Programmable In-memory Computing Circuit of Fast Hartley Transform	10
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	10
RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions	9
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	9
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	9
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	9
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	9
You Only Need Non-Hotspot: An Unsupervised Training-Free Method for Layout Hotspot Detection	9
Poor Man’s Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach	9
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	9
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	9
Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain	9
A Survey of Machine Learning Approaches in Logic Synthesis	9
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	9
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	9
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems	9
Training PPA Models for Embedded Memories on a Low-data Diet	9
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	9
FPGA Routing Congestion Prediction via Graph Learning-Aided Conditional GAN	8
MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures	8
ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures	8
LLM-assisted Bug Identification and Correction for Verilog HDL	8
Detecting Adversarial Examples Utilizing Pixel Value Diversity	8
Online Synthesis of MEDA Biochips with Area and Reliability-Aware Module Placement using Chamber-Less Virtual Topology	8
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	8
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	7
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	7
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	7
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	7
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	7
FLAG: F inding L ine A nomalies (in RTL code) with	7
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey	7
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	7
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction	7
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning	7
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	7
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	6
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	6

A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	6
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	6
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	6
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	6
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	6
Runtime Fault Localization in Deep Neural Network Accelerators	6
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	6
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	6
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	6
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	6
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	6
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	6
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA	6
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	6
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	6
Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage	6
Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set	5
Scan Chain Watermarking : A Graph Neural Network based approach	5
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	5
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	5
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	5
Structurally Secure Obfuscation: Assessing and Mitigating Structural Vulnerabilities in Circuits Obfuscation	5
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	5
Efficient and Effective E-graph-based Logic Optimization	5
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	5
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	5
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	5
Polling-Based Memory Interface	5
Breaking The Buffer : Covert Channel Attacks by Overrunning Buffer and Countermeasures	5
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	5
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	5
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	5
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	5
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization	5
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices	4
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	4
Efficient Test Chip Design via Smart Computation	4
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0	4
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together	4
Precise Learning-to-Rank Bug Localization Using Multi-Feature Fusion for Hardware Code	4
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	4
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains	4
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm	4
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking	4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs	4
High-level Synthesis Directives Design Optimization via Large Language Model	4
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits	4
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices	4
Synthesis of Clock Networks with a Mode-Reconfigurable Topology	4
Introduction to the Special Issue on Machine Learning for CAD/EDA	4
Introduction to Special Issue on Large Language Models for Electronic System Design Automation	4
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference	4
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling	4
Rescuing ReRAM-based Neural Computing Systems from Device Variation	3
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	3
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences	3
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware	3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks	3
On Enhancing the Security of Streaming Scan Network through Dual-Functional TDR	3
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators	3
Energy-aware Scheduling of Workflow Applications Towards Schedule Length Optimization in Heterogeneous Distributed Embedded Systems	3
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	3
An Improved MCTS Algorithm for Ordered Escape Routing of Differential Pair	3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication	3
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation	3
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers	3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework	3
Structured Dynamic Precision for Deep Neural Networks Quantization	3
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips	3
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	3
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing	3
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	3
Introduction to the Special Section on Energy-Efficient AI Chips	3

TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	3
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations	2
Sherlock: A Multi-Objective Design Space Exploration Framework	2
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	2
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits	2
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	2
AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing	2
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder	2
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits	2
CuPBoP: Making CUDA a Portable Language	2
Datapath Combinational Equivalence Checking With Hybrid Sweeping Engines and Parallelization	2
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming	2
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning	2
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	2
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development	2
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies	2
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	2
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis	2
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips	2
A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow	2
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack	2
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System	2
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement	2
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories	2
Unveiling Cross-checking Opportunities in Verilog Compilers	2
Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics	2
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	2
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	2
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models	2
Pareto Optimization of Analog Circuits Using Reinforcement Learning	2
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface	2
Towards Floating Point-Based AI Acceleration: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications	2
ARM-CO-UP: ARM COoperative Utilization of Processors	2
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction	2
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism	2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	2
FedTM: Federated ASIC Technology Mapping	2
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference	2
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization	2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	2
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM	2
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device	2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	2
PPD: A Portable and Highly Parallel Dispatching System for Deep Learning	2
iPO: Constant Liar Parameter Optimization for Placement with Representation and Transfer Learning	2
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation	2
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach	2
LOGIC: Logic Synthesis for Digital In-Memory Computing	2
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference	2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources	2
Global Placement Exploiting Soft 2D Regularity	2
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages	1
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration	1
Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation	1
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	1
Supporting Timing-related Metrics for Autonomous Driving Frameworks in CyberRT	1
Enhanced Compiler Technology for Software-based Hardware Fault Detection	1
CPSim: Simulation Toolbox for Security Problems in Cyber-Physical Systems	1
Toward a Human-Readable State Machine Extraction	1
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture	1
Automatic Test Pattern Generation for Robust Quantum Circuit Testing	1
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan	1
2D to 3D Placement for Monolithic Systems using Reinforcement Learning with Dynamic Hierarchical Cluster Assignment	1
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning	1
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC	1
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems	1
A Module-Level Configuration Methodology for Programmable Camouflaged Logic	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
A Variation Tolerant Write Assist Read Decoupled 9T SRAM Cell for Low Voltage Application	1
Memory-Throughput Trade-off for CNN-Based Applications at the Edge	1
Virtuoso : Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips	1
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	1
DDAM: D ata D istribution- A ware M apping of CNNs on Processing-In-Memory S	1
Test Point Insertion for Multi-Cycle Power-On Self-Test	1
A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values	1
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization	1
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement	1
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization	1
Global Interconnect Optimization	1
Design Automation Algorithms for the NP-Separate VLSI Design Methodology	1
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline	1
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis	1
TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET	1
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs	1
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration	1
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route	1
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior	1
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures	1
Routability-driven Power/Ground Network Optimization Based on Machine Learning	1
Mitigating Mode-switch through Run-time Computation of Response Time	1
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	1
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	1
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation	1
Test-Fleet Scheduling in Complex Validation and Production Environments	1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts	1