OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 5. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition	138
Reduced On-chip Storage of Seeds for Built-in Test Generation	115
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	61
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	36
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation	33
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	33
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	27
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	27
Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation	27
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	23
Graph Neural Networks for High-Level Synthesis Design Space Exploration	22
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	20
InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems	20
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning	19
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	19
DTGx2: Dual Target Diagnostic Test Generation	18
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	18
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	18
Introduction to the Special Issue on Embedded System Software/Tools	17
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	16
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks	15
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis	15
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	15
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	14
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	14

Scheduling Task Graph Applications on Preloaded Shared-Bus based Heterogeneous Platforms	13
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	13
Context-aware Data Augmentation for Hardware Code Fault localization	12
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	12
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models	12
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	12
Component Fault Diagnosability of Hierarchical Cubic Networks	12
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability	11
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	11
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	11
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	10
VeriGen: A Large Language Model for Verilog Code Generation	10
Programmable In-memory Computing Circuit of Fast Hartley Transform	10
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	10
RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions	9
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	9
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	9
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	9
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	9
You Only Need Non-Hotspot: An Unsupervised Training-Free Method for Layout Hotspot Detection	9
Poor Man’s Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach	9
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	9
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	9
Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain	9
A Survey of Machine Learning Approaches in Logic Synthesis	9
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	9
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	9
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems	9
Training PPA Models for Embedded Memories on a Low-data Diet	9
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	9
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	8
FPGA Routing Congestion Prediction via Graph Learning-Aided Conditional GAN	8
MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures	8
ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures	8
LLM-assisted Bug Identification and Correction for Verilog HDL	8
Detecting Adversarial Examples Utilizing Pixel Value Diversity	8
Online Synthesis of MEDA Biochips with Area and Reliability-Aware Module Placement using Chamber-Less Virtual Topology	8
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	7
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	7
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	7
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	7
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	7
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	7
FLAG: F inding L ine A nomalies (in RTL code) with	7
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey	7
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	7
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction	7
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning	7
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	6
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	6

MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	6
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	6
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	6
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	6
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	6
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	6
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	6
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	6
Runtime Fault Localization in Deep Neural Network Accelerators	6
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	6
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	6
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	6
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA	6
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	6
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	6
Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage	6
Breaking The Buffer : Covert Channel Attacks by Overrunning Buffer and Countermeasures	5
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	5
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	5
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	5
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	5
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization	5
Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set	5
Scan Chain Watermarking : A Graph Neural Network based approach	5
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	5
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	5
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	5
Structurally Secure Obfuscation: Assessing and Mitigating Structural Vulnerabilities in Circuits Obfuscation	5
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	5
Efficient and Effective E-graph-based Logic Optimization	5
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	5
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	5
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	5
Polling-Based Memory Interface	5