OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)

Article	Citations
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	100
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	71
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	50
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	25
Reduced On-chip Storage of Seeds for Built-in Test Generation	24
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	24
Graph Neural Networks for High-Level Synthesis Design Space Exploration	23
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	22
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	20
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation	19
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	18
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition	17
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	16
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	16
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	16
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	14
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	14
Component Fault Diagnosability of Hierarchical Cubic Networks	14
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	13
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	13
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis	12
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	12
DTGx2: Dual Target Diagnostic Test Generation	12
Introduction to the Special Issue on Embedded System Software/Tools	12
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks	12

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	11
VeriGen: A Large Language Model for Verilog Code Generation	10
Context-aware Data Augmentation for Hardware Code Fault localization	10
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	9
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	9
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs	9
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability	9
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	9
Poor Man's Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach	8
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	8
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision	8
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models	8
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	7
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	7
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	7
Programmable In-memory Computing Circuit of Fast Hartley Transform	7
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	7
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	7
ParTBC: Faster Estimation of Top- k Betweenness Centrality Vertices on GPU	7
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	7
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	7
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	6
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning	6
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	6
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	6
An Efficient Execution Framework of Two-Part Execution Scenario Analysis	6
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	6
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	6
Detecting Adversarial Examples Utilizing Pixel Value Diversity	6
Training PPA Models for Embedded Memories on a Low-data Diet	6
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips	6
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	6
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	6
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	6
LLM-assisted Bug Identification and Correction for Verilog HDL	6
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	5
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	5
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	5
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	5
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	5
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	5
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	5
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	5
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	5
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	5
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction	5
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	5

FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI	5
Learning-based Phase-aware Multi-core CPU Workload Forecasting	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs	4
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	4
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	4
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	4
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	4
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	4
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	4
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	4
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	4
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	4
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	4
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	4
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	4
Polling-Based Memory Interface	4
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices	4
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains	4
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	4
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization	4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	4
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	4
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	4
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	4