OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	192
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	89
Reduced On-chip Storage of Seeds for Built-in Test Generation	61
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	48
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	25
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	23
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	22
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	20
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	20
Graph Neural Networks for High-Level Synthesis Design Space Exploration	20
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	19
Machine Learning for Electronic Design Automation: A Survey	17
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	17
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	16
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	16
Component Fault Diagnosability of Hierarchical Cubic Networks	15
DTGx2: Dual Target Diagnostic Test Generation	15
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	13
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	13
Introduction to the Special Issue on Embedded System Software/Tools	12
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	12
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	12
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	11
Context-aware Data Augmentation for Hardware Code Fault localization	11
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	11

Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs	11
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	10
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	10
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	10
ParTBC: Faster Estimation of Top- k Betweenness Centrality Vertices on GPU	9
VeriGen: A Large Language Model for Verilog Code Generation	9
Programmable In-memory Computing Circuit of Fast Hartley Transform	9
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	9
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	8
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	8
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	8
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	8
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	8
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	7
Detecting Adversarial Examples Utilizing Pixel Value Diversity	7
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	7
Training PPA Models for Embedded Memories on a Low-data Diet	7
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision	7
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	7
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	7
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	7
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	7
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	6
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	6
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	6
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	6
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	6
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	6
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips	6
LLM-assisted Bug Identification and Correction for Verilog HDL	6
An Efficient Execution Framework of Two-Part Execution Scenario Analysis	6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	6
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	5
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	5
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	5
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	5
FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI	5
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	5
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	5
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	5
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	5
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	5
Learning-based Phase-aware Multi-core CPU Workload Forecasting	5
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	4

A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	4
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	4
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	4
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	4
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	4
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	4
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	4
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together	4
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	4
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	4
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	4
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	4
Polling-Based Memory Interface	4
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling	4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs	4
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm	3
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	3
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences	3
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation	3
Efficient Test Chip Design via Smart Computation	3
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	3
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains	3
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices	3
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips	3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework	3
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	3
Rescuing ReRAM-based Neural Computing Systems from Device Variation	3
Introduction to the Special Issue on Machine Learning for CAD/EDA	3
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking	3
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	3
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices	3
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	3
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing	3
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators	3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication	3
Structured Dynamic Precision for Deep Neural Networks Quantization	3
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	3
Synthesis of Clock Networks with a Mode-Reconfigurable Topology	3
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0	3