OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
Machine Learning for Electronic Design Automation: A Survey	108
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	45
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	28
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	25
Reconfigurable Network-on-Chip Security Architecture	19
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms	19
TAAL	18
MaxSense	17
SCRIPT	17
Adversarial Perturbation Attacks on ML-based CAD	17
Modular Neural Networks for Low-Power Image Classification on Embedded Devices	15
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	13
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging	13
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	13
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	12
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	12
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	11
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	11
Voltage-Based Covert Channels Using FPGAs	10
PREASC	10
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation	10
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT	10
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization	10
Directed Test Generation for Activation of Security Assertions in RTL Models	10
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks	10

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning	10
MNFTL	9
Algorithmic Fault Detection for RRAM-based Matrix Operations	9
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection	8
NoC Application Mapping Optimization Using Reinforcement Learning	8
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices	7
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET	7
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network	7
TransNet	7
Security Threat Analyses and Attack Models for Approximate Computing Systems	7
Towards Smarter Diagnosis	7
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications	7
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement	7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	7
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip	6
HeM3D	6
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	6
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	6
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	6
Graph Neural Networks for High-Level Synthesis Design Space Exploration	6
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory	6
NeuPow	6
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	6
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks	5
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	5
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production	5
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	5
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	5
Sherlock: A Multi-Objective Design Space Exploration Framework	5
Mitigating Negative Impacts of Read Disturb in SSDs	5
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs	4
Efficient Layout Hotspot Detection via Neural Architecture Search	4
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration	4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	4
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	4
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations	4
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs	4
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	4
Fine-grained Adaptive Testing Based on Quality Prediction	4
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	4
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems	4
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	4
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	4
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids	4
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	3
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity	3
Machine Learning for Statistical Modeling	3

A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
COPE	3
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory	3
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips	3
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	3
Improving FPGA-Based Logic Emulation Systems through Machine Learning	3
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation	3
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm	3
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing	3
Distance-aware Approximate Nanophotonic Interconnect	3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	3
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	3
Wire Load Oriented Analog Routing with Matching Constraints	3
Toward Taming the Overhead Monster for Data-flow Integrity	3
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration	3
Ising-FPGA	3
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles	3