OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)

Article	Citations
Introduction to the Special Section on Energy-Efficient AI Chips	175
CRM_BF:A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms	78
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	44
An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm	42
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	24
Introduction to the Special Issue on Approximate Systems	20
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures	19
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	16
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors	16
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	16
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	16
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity	15
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion	15
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	15
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	14
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	13
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	13
Worst-case Power Integrity Prediction Using Convolutional Neural Network	12
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	11
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction	11
Deadline and Period Assignment for Guaranteeing Timely Response of the Cyber-Physical System	10
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	10
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	10
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing	9
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	9

Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay	9
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits	9
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning	9
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking	9
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology	8
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM	8
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	8
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement	8
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	7
Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems	7
Applying reinforcement learning to learn best net to rip and re-route in global routing	7
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	7
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware	7
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers	7
Reduced On-chip Storage of Seeds for Built-in Test Generation	7
E ² -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition	6
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	6
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis	6
Graph Neural Networks for High-Level Synthesis Design Space Exploration	6
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	5
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization	5
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	5
Machine Learning for Electronic Design Automation: A Survey	5
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	5
Component Fault Diagnosability of Hierarchical Cubic Networks	5
Load Balanced PIM-Based Graph Processing	5
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	5
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level	5
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference	5
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	5
Data Privacy Made Easy: Enhancing Applications with Homomorphic Encryption	5
Test Point Insertion for Multi-Cycle Power-On Self-Test	4
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	4
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs	4
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device	4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	4
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension	4
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs	4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	4
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	4
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	4
Unveiling Cross-checking Opportunities in Verilog Compilers	4
A Fast Optimal Double-row Legalization Algorithm	4
A Constructive Approach for Threshold Function Identification	4
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	4
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	4
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability	4
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization	3
DeLoSo: Detecting Logic Synthesis Optimization Faults Based on Configuration Diversity	3

Adversarial Circuit Rewriting against Graph Neural Network-based Operator Detection	3
On-chip ESD Protection Design Methodologies by CAD Simulation	3
Automatic Test Pattern Generation for Robust Quantum Circuit Testing	3
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation	3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	3
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	3
Routability-driven Power/Ground Network Optimization Based on Machine Learning	3
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	3
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	3
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	3
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips	3
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization	3
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis	3
ZoneTrace: Zone Monitoring Tool for F2FS on ZNS SSDs	3
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	3
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	3
Toward a Human-Readable State Machine Extraction	3
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis	3
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	3
D ³ PBO: D ynamic D omain D ecomposition-based P	3
Introduction to the Special Issue on Embedded System Software/Tools	3
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories	3
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices	3
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips	3
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	3
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes	3
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	3
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems	3