ACM Transactions on Embedded Computing Systems

Papers
(The median citation count of ACM Transactions on Embedded Computing Systems is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)
ArticleCitations
Model-based Toolchain for Core Flight System (cFS) Embedded Systems92
REC: REtime Convolutional Layers to Fully Exploit Harvested Energy for ReRAM-based CNN Accelerators71
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators68
SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation67
Using Learning with Rounding to Instantiate Post-Quantum Cryptographic Algorithms66
A Comprehensive Survey on Deep Learning-based Predictive Maintenance63
Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning63
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra62
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems59
A Novel Lattice-Based Fault Injection Attack Targeting the Nonce in the SM2 Digital Signature Algorithm56
Optimizing AES-GCM on 32-Bit ARM Cortex-M4 Microcontrollers: Fixslicing and FACE-Based Approach50
Directed Real-time Linux Fuzzing with Configuration Awareness49
CapDYN : Adaptive Self-Scaling Energy Storage for Powering Batteryless IoT45
A Design of Network Reconfigurable Universal CNN Accelerator Based on FPGA42
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices41
Graph Transformations for Memory Peak Minimization by Scheduling41
TAFP-ViT: A Transformer Accelerator via QKV Computational Fusion and Adaptive Pruning for Vision Transformer40
IoV-Fog-Assisted Framework for Accident Detection and Classification39
More Is Less: Model Augmentation for Intermittent Deep Inference36
PolyARBerNN: A Neural Network Guided Solver and Optimizer for Bounded Polynomial Inequalities34
WasmAndroid: A Cross-Platform Runtime for Native Programming Languages on Android34
Large or Small: Harnessing the Erase Duality of Emerging Bit-Alterable NAND Flash to Suppress Tail Latency34
A Self-Sustained CPS Design for Reliable Wildfire Monitoring32
VoxDepth : Rectification of Depth Images on Edge Devices31
Distributed Task Offloading and Resource Purchasing in NOMA-Enabled Mobile Edge Computing: Hierarchical Game Theoretical Approaches30
Neural Abstraction-Based Controller Synthesis and Deployment29
SENTRY: Protecting System-on-Chip Designs against Supply-Chain Attacks29
SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells28
FSIMR: File-system-aware Data Management for Interlaced Magnetic Recording27
Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency27
Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems26
Mining Hyperproperties using Temporal Logics24
Automatic Generation of Resource and Accuracy Configurable Processing Elements24
Formally Verified Loop-Invariant Code Motion and Assorted Optimizations24
DyCo: Dynamic, Contextualized AI Models24
Formal Modeling of Hybrid System Based on Semi-continuous Colored Petri Net: A Case Study of Adaptive Cruise Control System24
DynHaMo: Dynamic Hardware-Based Monitoring Dedicated to Attacks Detection23
Unlocking the Full Potential of Dual-Interface SSDs: A Comprehensive Hardware and Software Perspective22
Star-Set Based Efficient Reachable Set Computation of Anytime Sensing-Based Neural Network-Controlled Dynamical Systems22
Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators22
CADAS: Communication-Aware Dynamic Scheduler on CGRAs for Large-Volume and Real-Time Processing21
Scalable Binary Neural Network Applications in Oblivious Inference21
An Efficient and Flexible Stochastic CGRA Mapping Approach21
Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Coarsely-quantized Log-gradient Input Images21
Towards Building Verifiable CPS using Lingua Franca20
Performance Modeling of Computer Vision-based CNN on Edge GPUs20
Securing Pacemakers Using Runtime Monitors over Physiological Signals19
CARIn: Constraint-Aware and Responsive Inference on Heterogeneous Devices for Single- and Multi-DNN Workloads18
A Write-Related and Read-Related DRAM Allocation Strategy Inside Solid-State Drives (SSDs)18
Supervisory Control for Dynamic Feature Configuration in Product Lines18
Unleashing Cross-Domain Potential: Side-Channel Analysis with Autoencoder for Domain Adaptation18
EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator17
Evolution Function Based Reach-Avoid Verification for Time-varying Systems with Disturbances17
SecuPilot: A Security Coprocessor-Integrated Platform for Autonomous UAV Security16
Federated Self-training for Semi-supervised Audio Recognition16
Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization16
RPFF-PA : Reliable and Parallel Fault-tolerant Framework for Path Latency Reduction Deployed in Register Arrays16
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators16
Boosting Cryptographic ICs’ Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths16
Multi-Compression Scale DNN Inference Acceleration based on Cloud-Edge-End Collaboration16
FC-GPU: Feedback Control GPU Scheduling for Real-time Embedded Systems16
Criticality-aware Monitoring and Orchestration for Containerized Industry 4.0 Environments15
PEak: A Single Source of Truth for Hardware Design and Verification15
Middleware for Distributed Applications in a LoRa Mesh Network15
Specifying and Compiling Scalable Networks of Actors for Software and Hardware Platforms15
Reaction Latency Analysis of Message Synchronization in Edge-assisted Autonomous Driving15
DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips15
BASS: Safe Deep Tissue Optical Sensing for Wearable Embedded Systems14
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes14
Optimus: An Operator Fusion Framework for Deep Neural Networks14
Introduction to the Special Issue on Accelerating AI on the Edge – Part 113
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements13
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators13
Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System13
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories13
XimSwap: Many-to-Many Face Swapping for TinyML12
DiGiT: A Diffusion-based Modular Geophysical Toolkit for On-device Multi-modal Data Generation12
Elements of Timed Pattern Matching12
A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers12
Analog In-memory Circuit Design of Polynomial Multiplication for Lattice Cipher Acceleration Application12
DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors12
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators12
Global Scheduling of Weakly-Hard Real-Time Tasks using Job-Level Priority Classes11
Leveraging Computational Storage for Power-Efficient Distributed Data Analytics11
A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits11
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection11
RTPL: A Real-Time Communication Protocol for LoRa Network11
ZIP-CNN: Design Space Exploration for CNN Implementation within a MCU11
HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL11
Latency-Aware Pruning and Quantization of Self-Supervised Speech Transformers for Edge Devices11
Efficient and Robust Edge AI: Software, Hardware, and the Co-design11
Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems10
VADF: V ersatile A pproximate D ata F ormats for Energy-Efficient Computing10
Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures10
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs10
TreeHouse: An MLIR-based Compilation Flow for Real-Time Tree-based Inference10
Probabilistic Reaction Time Analysis10
Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator10
A Load-Balanced Collaborative Repair Algorithm for Single-Disk Failures in Erasure Coded Storage Systems10
Wireless Perceptual Space Modeling Method for Cross-Domain Human Activity Recognition9
Hierarchical Resource Orchestration Framework for Real-time Containers9
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems9
Dataflow Driven Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems9
Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy9
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge9
Faster Implementation of Ideal Lattice-Based Cryptography Using AVX5129
DynO: Dynamic Onloading of Deep Neural Networks from Cloud to Device9
Domain-Specific Architectures: Research Problems and Promising Approaches9
A Tree-Shaped Tableau for Checking the Satisfiability of Signal Temporal Logic with Bounded Temporal Operators9
RegKey: A Register-based Implementation of ECC Signature Algorithms Against One-shot Memory Disclosure9
An Efficient CNN Accelerator for Low-Cost Edge Systems9
Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention9
CABARRE: Request Response Arbitration for Shared Cache Management9
Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis9
Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques9
Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks9
????????????????????????: Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System8
FT-DAG: An Efficient Full-Topology DAG Generator with Controllable Parameters8
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures Enabled by Non-Bendable Glass Interposer8
Rectifying Skewed Kernel Page Reclamation in Mobile Devices for Improving User-Perceivable Latency8
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration8
A Survey of Blockchain Data Management Systems8
HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography8
Optimal Control for Industrial Multi-Component CPS via Path-Encoding-Based Joint Optimization8
Robust Embedded Autonomous Driving Positioning System Fusing LiDAR and Inertial Sensors8
SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks8
Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process8
Code Generation for Neural Networks Based on Fixed-point Arithmetic8
Design Flow for Scheduling Spiking Deep Convolutional Neural Networks on Heterogeneous Neuromorphic System-on-chip8
Regular Composite Resource Partitioning and Reconfiguration in Open Systems8
Selective Subarray Isolation for Mitigating RowHammer Attack8
Challenges and Opportunities of Security-Aware EDA8
Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium8
An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA8
SPHINCSLET: An Area-Efficient Accelerator for the Full SPHINCS+ Digital Signature Algorithm8
A Compact and Parallel Swap-Based Shuffler Based on Butterfly Network and Its Complexity Against Side Channel Analysis8
Efficient Addition-Based Sparse GEMM for Fast Ternary Large Language Model Inference on Edge Devices8
HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost7
Optimal Checkpointing Strategy for Real-time Systems with Both Logical and Timing Correctness7
Attack-resilient Fusion of Sensor Data with Uncertain Delays7
TimelyNet: Adaptive Neural Architecture for Autonomous Driving with Dynamic Deadline7
Register Blocking: A Source-to-Source Analytical Modelling Approach for Affine Loop Kernels7
DaCapo: An On-Device Learning Scheme for Memory-Constrained Embedded Systems7
MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation7
Improving Robustness in IoT Malware Detection through Execution Order Analysis7
MaGrIP: Magnitude and Gradient-Informed Pruning for Task-Agnostic Large Language Models7
A Configurable CRYSTALS-Kyber Hardware Implementation with Side-Channel Protection7
Virtual Environment Model Generation for CPS Goal Verification using Imitation Learning7
Software Optimization and Design Methodology for Low Power Computer Vision Systems7
An Investigation on Hardware-Aware Vision Transformer Scaling7
GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators7
RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing7
Introduction to the Special Issue on Specification and Design Languages7
ASTRA: A Stochastic Transformer Neural Network Accelerator with Silicon Photonics7
RAD-FS: Remote Timing and Power SCA Security in DVFS-augmented Ultra-Low-Power Embedded Systems7
Benchmarking and Configuring Security Levels in Intermittent Computing7
SentinelEdge: An Attention-Based Defense for Real-Time Mitigation of Adversarial Thermal Manipulations in System-on-Chips7
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs7
High-Level Approaches to Hardware Security: A Tutorial7
CrossTalk : Making Low-Latency Fault Tolerance Cheap by Exploiting Redundant Networks7
Verified Compilation of Synchronous Dataflow with State Machines7
Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression7
Optimal Synthesis of Robust IDK Classifier Cascades6
SensiX++: Bringing MLOps and Multi-tenant Model Serving to Sensory Edge Devices6
PReFeR : P hysically Re lated F unction bas e d R 6
Energy-Efficient Approximate Edge Inference Systems6
A Hybrid Target Selection Model of Functional Safety Compliance for Autonomous Driving System6
Protection Window Based Security-Aware Scheduling against Schedule-Based Attacks6
REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems6
AMULET: A Mutation Language Enabling Automatic Enrichment of SysML Models6
CIM: A Novel Clustering-based Energy-Efficient Data Imputation Method for Human Activity Recognition6
Block Walsh–Hadamard Transform-based Binary Layers in Deep Neural Networks6
Trustworthy Autonomous System Development6
Deadline-Aware Task Offloading for Vehicular Edge Computing Networks Using Traffic Light Data6
A Hybrid Sparse-dense Defensive DNN Accelerator Architecture against Adversarial Example Attacks6
Resource-demand Estimation for Edge Tensor Processing Units6
A Constructive State-based Semantics and Interpreter for a Synchronous Data-flow Language with State Machines6
Reconfigurable System-on-Chip Architectures for Robust Visual SLAM on Humanoid Robots6
Tutorial: Toward Robust Deep Learning against Poisoning Attacks6
CAN Bus Intrusion Detection Based on Auxiliary Classifier GAN and Out-of-distribution Detection6
A Unified Approach to a Secure and Lightweight Mutual Authentication Protocol Using Pre-Characterized COTS SRAM ICs for IoT Applications6
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems6
Methods to Realize Preemption in Phased Execution Models5
Toward Next Generation Quantum-Safe eIDs and eMRTDs: A Survey5
Rasco: Resource Allocation and Scheduling Co-design for DAG Applications on Multicore5
Reliability Assessment and Safety Arguments for Machine Learning Components in System Assurance5
LiteHash: Hash Functions for Resource-Constrained Hardware5
NAVIDRO, a CARES architectural style for configuring drone co-simulation5
Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads5
Dynamic Cluster Head Selection in WSN5
A Fall Detection Network by 2D/3D Spatio-temporal Joint Models with Tensor Compression on Edge5
LazyTick: Lazy and Efficient Management of Job Release in Real-Time Operating Systems5
Exploring Inevitable Waypoints for Unsolvability Explanation in Hybrid Planning Problems5
AxLEA: Approximate ARX-based Lightweight Encryption Algorithm for Resource Constrained Devices5
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors5
End-To-End Latency of Cause-Effect Chains: A Tutorial5
Deep Q-Learning-Based Mobile Charger Path Planning in Wireless Powered Communication Networks5
FARRE: Fairness Aware Request Response Arbitration in Shared Caches5
Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators5
Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF5
Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration5
Transfer Schedulability in Periodic Real-Time Systems5
CNN-based Robust Sound Source Localization with SRP-PHAT for the Extreme Edge5
A Design Flow Based on Docker and Kubernetes for ROS-based Robotic Software Applications5
A Secure and Efficient Framework for Outsourcing Large-scale Matrix Determinant and Linear Equations5
ACM TECS Special Issue on Embedded System Security Tutorials5
ETAP: Energy-aware Timing Analysis of Intermittent Programs5
Special Issue on Open Hardware for Embedded System Security and Cryptography5
EASYR: E nergy-Efficient A daptive Sy stem R econfiguration for Dynamic Dead5
GHOST: A Graph Neural Network Accelerator using Silicon Photonics4
ObNoCs : Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks4
SecureRide: Detecting Safety-Threatening Behavior of E-Scooters Using Battery Information4
Cumulative-Time Signal Temporal Logic4
CRIMP: C ompact & R eliable DNN Inference on I n- M emory 4
Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems4
Grasp-HGN: Grasping the Unexpected4
FirmCAN: Sensitive CAN Knowledge Leakage from Automotive ECUs4
Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain4
P 2 SDS : A Polynomial-Time Pattern-Guided Stable Dynamic Scheduling for W4
Diwall: A Lightweight Host Intrusion Detection System Against Jamming and Packet Injection Attacks4
Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies4
TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor4
Synchronised Shared Memory and Model Checking4
Metareasoning for Edge-Cloud Collaborative LLM Planning for Efficient Autonomous Navigation4
Hardware Area Efficient and Real-Time FPGA Implementation of PHMMRGB.4
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs4
Risk of Stochastic Systems for Temporal Logic Specifications4
Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs4
Survey of Control-flow Integrity Techniques for Real-time Embedded Systems4
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators4
Stochastic Analysis of Control Systems Subject to Communication and Computation Faults4
Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration4
SHARP: SHARing-Aware Cache Writeback byPass4
An Approach to the Systematic Characterization of Multitask Accelerated CNN Inference in Edge MPSoCs4
SLEXNet: Adaptive Inference Using Slimmable Early Exit Neural Networks4
TyBox: An Automatic Design and Code Generation Toolbox for TinyML Incremental On-Device Learning4
Re-thinking Memory-Bound Limitations in CGRAs4
COMFORT: A Continual Fine-Tuning Framework for Foundation Models Targeted at Consumer Healthcare4
Intermediary Output Caching for Diffusion Model-Based Text-to-Image GenAI Services in Edge Computing Networks4
Side-channel Analysis of Lattice-based Post-quantum Cryptography: Exploiting Polynomial Multiplication4
Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory4
Post-Quantum Signatures on RISC-V with Hardware Acceleration3
Side-channel and Fault-injection attacks over Lattice-based Post-quantum Schemes (Kyber, Dilithium): Survey and New Results3
FLIP2M: Flexible Intra-layer Parallelism and Inter-layer Pipelining for Multi-model AR/VR Workloads3
Characterizing Parameter Scaling with Quantization for Deployment of CNNs on Real-Time Systems3
Modeling and Analysis of ETC Control System with Colored Petri Net and Dynamic Slicing3
PredATW: Predicting the Asynchronous Time Warp Latency For VR Systems3
EMS-i : An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference3
ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer3
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators3
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