ACM Transactions on Embedded Computing Systems

Papers
(The TQCC of ACM Transactions on Embedded Computing Systems is 7. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
Model-based Toolchain for Core Flight System (cFS) Embedded Systems81
REC: REtime Convolutional Layers to Fully Exploit Harvested Energy for ReRAM-based CNN Accelerators61
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators60
Holistic Resource Allocation Under Federated Scheduling for Parallel Real-time Tasks58
SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation58
Introduction to the Special Issue on Memory and Storage Systems for Embedded and IoT Applications56
CapDYN : Adaptive Self-Scaling Energy Storage for Powering Batteryless IoT54
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra54
Optimizing AES-GCM on 32-Bit ARM Cortex-M4 Microcontrollers: Fixslicing and FACE-Based Approach48
Directed Real-time Linux Fuzzing with Configuration Awareness45
Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning44
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems44
A Comprehensive Survey on Deep Learning-based Predictive Maintenance40
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices37
Graph Transformations for Memory Peak Minimization by Scheduling35
A Novel Lattice-Based Fault Injection Attack Targeting the Nonce in the SM2 Digital Signature Algorithm35
PolyARBerNN: A Neural Network Guided Solver and Optimizer for Bounded Polynomial Inequalities34
WasmAndroid: A Cross-Platform Runtime for Native Programming Languages on Android34
More Is Less: Model Augmentation for Intermittent Deep Inference34
A Self-Sustained CPS Design for Reliable Wildfire Monitoring33
Large or Small: Harnessing the Erase Duality of Emerging Bit-Alterable NAND Flash to Suppress Tail Latency30
VoxDepth : Rectification of Depth Images on Edge Devices27
TAFP-ViT: A Transformer Accelerator via QKV Computational Fusion and Adaptive Pruning for Vision Transformer27
IoV-Fog-Assisted Framework for Accident Detection and Classification26
Distributed Task Offloading and Resource Purchasing in NOMA-Enabled Mobile Edge Computing: Hierarchical Game Theoretical Approaches25
Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency25
Neural Abstraction-Based Controller Synthesis and Deployment25
Securing Pacemakers Using Runtime Monitors over Physiological Signals24
Towards Building Verifiable CPS using Lingua Franca24
FSIMR: File-system-aware Data Management for Interlaced Magnetic Recording24
Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems23
Formally Verified Loop-Invariant Code Motion and Assorted Optimizations22
Mining Hyperproperties using Temporal Logics21
Formal Modeling of Hybrid System Based on Semi-continuous Colored Petri Net: A Case Study of Adaptive Cruise Control System21
Automatic Generation of Resource and Accuracy Configurable Processing Elements20
DynHaMo: Dynamic Hardware-Based Monitoring Dedicated to Attacks Detection20
DyCo: Dynamic, Contextualized AI Models20
Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Coarsely-quantized Log-gradient Input Images20
Scalable Binary Neural Network Applications in Oblivious Inference18
Unlocking the Full Potential of Dual-Interface SSDs: A Comprehensive Hardware and Software Perspective18
An Efficient and Flexible Stochastic CGRA Mapping Approach18
Star-Set Based Efficient Reachable Set Computation of Anytime Sensing-Based Neural Network-Controlled Dynamical Systems18
Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators18
Performance Modeling of Computer Vision-based CNN on Edge GPUs18
Evolution Function Based Reach-Avoid Verification for Time-varying Systems with Disturbances17
Middleware for Distributed Applications in a LoRa Mesh Network17
Supervisory Control for Dynamic Feature Configuration in Product Lines17
Reaction Latency Analysis of Message Synchronization in Edge-assisted Autonomous Driving17
EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator17
PEak: A Single Source of Truth for Hardware Design and Verification17
SecuPilot: A Security Coprocessor-Integrated Platform for Autonomous UAV Security16
RPFF-PA : Reliable and Parallel Fault-tolerant Framework for Path Latency Reduction Deployed in Register Arrays16
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators16
FC-GPU: Feedback Control GPU Scheduling for Real-time Embedded Systems16
Boosting Cryptographic ICs’ Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths16
Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization16
Specifying and Compiling Scalable Networks of Actors for Software and Hardware Platforms15
Criticality-aware Monitoring and Orchestration for Containerized Industry 4.0 Environments14
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory14
Federated Self-training for Semi-supervised Audio Recognition14
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes14
Multi-Compression Scale DNN Inference Acceleration based on Cloud-Edge-End Collaboration13
Optimus: An Operator Fusion Framework for Deep Neural Networks13
A Write-Related and Read-Related DRAM Allocation Strategy Inside Solid-State Drives (SSDs)13
BASS: Safe Deep Tissue Optical Sensing for Wearable Embedded Systems13
CARIn: Constraint-Aware and Responsive Inference on Heterogeneous Devices for Single- and Multi-DNN Workloads13
DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips13
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements12
Efficient and Robust Edge AI: Software, Hardware, and the Co-design12
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories12
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators12
DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors12
Introduction to the Special Issue on Accelerating AI on the Edge – Part 111
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators11
ZIP-CNN: Design Space Exploration for CNN Implementation within a MCU11
Latency-Aware Pruning and Quantization of Self-Supervised Speech Transformers for Edge Devices11
Leveraging Computational Storage for Power-Efficient Distributed Data Analytics11
Analog In-memory Circuit Design of Polynomial Multiplication for Lattice Cipher Acceleration Application11
Telomere: Real-Time NAND Flash Storage11
Elements of Timed Pattern Matching11
Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System11
DiGiT: A Diffusion-based Modular Geophysical Toolkit for On-device Multi-modal Data Generation11
Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy10
An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory10
XimSwap: Many-to-Many Face Swapping for TinyML10
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems10
A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits10
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection10
A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers10
HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL9
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs9
Wireless Perceptual Space Modeling Method for Cross-Domain Human Activity Recognition9
Hierarchical Resource Orchestration Framework for Real-time Containers9
CABARRE: Request Response Arbitration for Shared Cache Management9
Probabilistic Reaction Time Analysis9
TreeHouse: An MLIR-based Compilation Flow for Real-Time Tree-based Inference9
RegKey: A Register-based Implementation of ECC Signature Algorithms Against One-shot Memory Disclosure9
VADF: V ersatile A pproximate D ata F ormats for Energy-Efficient Computing9
Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator9
Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems9
A Load-Balanced Collaborative Repair Algorithm for Single-Disk Failures in Erasure Coded Storage Systems9
Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures9
Faster Implementation of Ideal Lattice-Based Cryptography Using AVX5129
Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks8
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge8
Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis8
Challenges and Opportunities of Security-Aware EDA8
SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks8
Optimal Control for Industrial Multi-Component CPS via Path-Encoding-Based Joint Optimization8
DynO: Dynamic Onloading of Deep Neural Networks from Cloud to Device8
RTPL: A Real-Time Communication Protocol for LoRa Network8
Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention8
A Tree-Shaped Tableau for Checking the Satisfiability of Signal Temporal Logic with Bounded Temporal Operators8
Robust Embedded Autonomous Driving Positioning System Fusing LiDAR and Inertial Sensors8
Selective Subarray Isolation for Mitigating RowHammer Attack8
Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques8
????????????????????????: Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System8
An Efficient CNN Accelerator for Low-Cost Edge Systems8
Domain-Specific Architectures: Research Problems and Promising Approaches8
Dataflow Driven Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems8
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures Enabled by Non-Bendable Glass Interposer8
Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium8
Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process8
An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA7
HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography7
GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators7
Design Flow for Scheduling Spiking Deep Convolutional Neural Networks on Heterogeneous Neuromorphic System-on-chip7
Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression7
Software Optimization and Design Methodology for Low Power Computer Vision Systems7
DaCapo: An On-Device Learning Scheme for Memory-Constrained Embedded Systems7
HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost7
Rectifying Skewed Kernel Page Reclamation in Mobile Devices for Improving User-Perceivable Latency7
A Compact and Parallel Swap-Based Shuffler Based on Butterfly Network and Its Complexity Against Side Channel Analysis7
An Investigation on Hardware-Aware Vision Transformer Scaling7
High-Level Approaches to Hardware Security: A Tutorial7
SPHINCSLET: An Area-Efficient Accelerator for the Full SPHINCS+ Digital Signature Algorithm7
Virtual Environment Model Generation for CPS Goal Verification using Imitation Learning7
A Survey of Blockchain Data Management Systems7
FT-DAG: An Efficient Full-Topology DAG Generator with Controllable Parameters7
Regular Composite Resource Partitioning and Reconfiguration in Open Systems7
Code Generation for Neural Networks Based on Fixed-point Arithmetic7
Register Blocking: A Source-to-Source Analytical Modelling Approach for Affine Loop Kernels7
Attack-resilient Fusion of Sensor Data with Uncertain Delays7
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration7
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs7
TimelyNet: Adaptive Neural Architecture for Autonomous Driving with Dynamic Deadline7
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