OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Architecture and Code Optimization is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
SMAUG	33
IR2V EC	32
Domain-Specific Multi-Level IR Rewriting for GPU	25
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures	21
Grus	20
ArmorAll	20
A Black-box Monitoring Approach to Measure Microservices Runtime Performance	19
Compiler Support for Sparse Tensor Computations in MLIR	18
LLOV	17
PERI	17
PAVER	17
Dynamic Precision Autotuning with TAFFO	16
A Case For Intra-rack Resource Disaggregation in HPC	13
Inter-kernel Reuse-aware Thread Block Scheduling	13
SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms	13
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	12
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators	12
Securing Branch Predictors with Two-Level Encryption	11
Efficient Auto-Tuning of Parallel Programs with Interdependent Tuning Parameters via Auto-Tuning Framework (ATF)	11
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications	11
A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels	11
AsynGraph	10
OD-SGD	10
Gem5-X	10
KernelFaRer	10

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM	10
Exploiting Parallelism Opportunities with Deep Learning Frameworks	10
EchoBay	9
GEVO	9
PolyDL	9
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication	9
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs	8
On the Anatomy of Predictive Models for Accelerating GPU Convolution Kernels and Beyond	8
Performance Evaluation of Intel Optane Memory for Managed Workloads	8
Schedule Synthesis for Halide Pipelines on GPUs	8
GRAM	8
GPU Fast Convolution via the Overlap-and-Save Method in Shared Memory	8
Low-precision Logarithmic Number Systems	8
Architecting Optically Controlled Phase Change Memory	8
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems	8
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization	7
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes	7
Bayesian Optimization for Efficient Accelerator Synthesis	7
A Conflict-free Scheduler for High-performance Graph Processing on Multi-pipeline FPGAs	7
Scale-out Systolic Arrays	6
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints	6
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model	6
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer	6
HeapCheck: Low-cost Hardware Support for Memory Safety	5
Understanding Cache Compression	5
FastPath_MP	5
Gretch	5
Cooperative Software-hardware Acceleration of K-means on a Tightly Coupled CPU-FPGA System	5
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006	5
Autotuning Convolutions Is Easier Than You Think	5
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration	5
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs	5
LargeGraph	5
SIMT-X	5
E-BATCH: Energy-Efficient and High-Throughput RNN Batching	5
GraphPEG	5
MC-DeF	5
Refresh Triggered Computation	5
Energy-efficient In-Memory Address Calculation	5
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache	4
GraphAttack	4
On Architectural Support for Instruction Set Randomization	4
Practical Software-Based Shadow Stacks on x86-64	4
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory	4
Performance and Power Prediction for Concurrent Execution on GPUs	4
MemSZ	4
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks	4
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators	4
SPX64	4
GPU Domain Specialization via Composable On-Package Architecture	4

MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation	4
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors	4
Zeroploit	4