ACM Transactions on Architecture and Code Optimization

Papers
(The TQCC of ACM Transactions on Architecture and Code Optimization is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
Performance, Energy and NVM Lifetime-Aware Data Structure Refinement and Placement for Heterogeneous Memory Systems49
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power38
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency35
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization27
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework24
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes24
ESMPC: An Efficient Neural Network Training Framework for Secure Two- and Three-Party Computation23
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators23
Accelerating Verifiable Queries over Blockchain Database System Using Processing-in-memory21
Intra-request Lag-aware Cache Management to Enhance I/O Responsiveness of SSDs20
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence19
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication17
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation17
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor16
A Concise Concurrent B + -Tree for Persistent Memory16
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework15
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage15
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs13
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign13
Source Matching and Rewriting for MLIR Using String-Based Automata13
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster12
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product12
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler11
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments11
Accelerating Video Captioning on Heterogeneous System Architectures11
MLKAPS: Machine Learning and Adaptive Sampling for HPC Kernel Auto-tuning10
FlashGEMM: Optimizing Sequences of Matrix Multiplication by Exploiting Data Reuse on CPUs10
Flexible and Effective Object Tiering for Heterogeneous Memory Systems10
SnsBooster: Enhancing Sampling-based μ Arch Evaluation Efficiency through Online Performance Sensitivity Analysis9
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems9
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs9
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs9
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy9
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning9
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism9
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks8
COX : Exposing CUDA Warp-level Functions to CPUs8
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction8
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks8
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture8
Accelerating Parallel Structures in DNNs via Parallel Fusion and Operator Co-Optimization8
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping8
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies8
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults8
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions8
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks8
Towards high scalability and fine-grained parallelism on distributed HPC platforms8
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems7
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption7
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing7
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing7
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis7
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching7
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models7
SimTrace: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis7
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion7
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy7
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals7
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service7
Pac-PIM: A Parallel Communication Framework for Commodity Processing-in-memory Systems6
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs6
Mobile-3DCNN: An Acceleration Framework for Ultra-Real-Time Execution of Large 3D CNNs on Mobile Devices6
Towards Optimizing Learned Index for High Performance, Memory Efficiency and NUMA Awareness6
HiSo: Co-optimizing the Intra-layer and Inter-layer Scheduling Schemes with the Hybrid Data Flow for PIM Architectures6
CGCGraph: Efficient CPU-GPU Co-execution for Concurrent Dynamic Graph Processing6
RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors6
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes6
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs6
gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography6
A Stable Idle Time Detection Platform for Real I/O Workloads6
EDAS: Enabling Fast Data Loading for GPU Serverless Computing6
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs5
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage5
Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors5
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation5
Efficient and Scalable Hybrid Parallelization of Unstructured Computational Fluid Dynamics with Geometric Multigrid5
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing5
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations5
Lightweight Code Outlining for Android Applications5
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language5
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks5
Improving Utilization of Dataflow Unit for Multi-Batch Processing5
WIPE: A Write-Optimized Learned Index for Persistent Memory5
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling5
Abakus: Accelerating k -mer Counting with Storage Technology4
Scale-out Systolic Arrays4
Consequence-based Clustered Architecture4
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation4
Address/Data Instruction Steering in Clustered General Purpose Processors4
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs4
Architecting Optically Controlled Phase Change Memory4
CASHT: Contention Analysis in Shared Hierarchies with Thefts4
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications4
Iterating Pointers: Enabling Static Analysis for Loop-based Pointers4
Capability-Based Efficient Data Transmission Mechanism for Serverless Computing4
Rethinking Variable-Length Encoding: Exploiting Bit Sparsity for Parallel Decoding in LLM Accelerators4
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication4
RaKV: A Write-Optimized LSM Store for Cloud Block Storage with Robust SLA4
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources4
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU4
MetaEC: An Efficient and Resilient Erasure-Coded KV Store on Disaggregated Memory4
TSN Cache: Exploiting Data Localities in Graph Computing Applications4
Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core4
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