OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 50. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	294
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	227
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	175
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	165
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs	128
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	128
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	120
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	119
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	119
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	105
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	101
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	97
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	93
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	88
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	84
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	82
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	80
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	79
IEEE Open Access Publishing	78
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	76
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	75
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	72
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	71
TechRxiv: Share Your Preprint Research with the World!	69
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	68

Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	65
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	65
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	64
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	63
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	63
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	62
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	60
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	59
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	58
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	58
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	57
A Compact One-Transistor-Multiple-RRAM Characterization Platform	57
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	55
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	55
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	54
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	54
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS	54
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	54
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	53
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	53
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	53
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	52
Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application	52
Fast Algorithms for Resistance Distances on Signed Graphs	50
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	50
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	50
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	50
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	50
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning	50