OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 50. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	181
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	170
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs	140
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	139
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	130
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	126
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	123
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	109
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	99
IEEE Open Access Publishing	93
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	89
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	84
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	84
TechRxiv: Share Your Preprint Research with the World!	82
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	82
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	79
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	74
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	72
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	68
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	68
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	67
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	67
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	67
A Compact One-Transistor-Multiple-RRAM Characterization Platform	67
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	66

Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	65
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	63
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	63
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	62
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	61
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	60
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	60
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	59
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	59
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	58
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	58
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	57
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	57
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	56
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	55
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	55
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	55
Fast Algorithms for Resistance Distances on Signed Graphs	55
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	55
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	55
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	54
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	53
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	52
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	51
Neuromorphic Dynamics of Chua Corsage Memristor	50
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	50