OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 49. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	173
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	155
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	154
IEEE Open Access Publishing	144
TechRxiv: Share Your Preprint Research with the World!	105
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	102
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	99
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	94
A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation	84
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	84
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	81
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	78
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	76
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	75
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	74
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	72
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	72
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	70
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	68
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	66
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	65
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	65
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	65
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	64
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	62

Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	62
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	61
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	61
Fast Algorithms for Resistance Distances on Signed Graphs	61
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	59
Frequency Response Model for Power Systems Including HVDC-Connected Offshore Wind Power With Communication-Free Frequency Control	59
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	59
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	58
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	57
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	56
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	55
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	55
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	55
A Compact One-Transistor-Multiple-RRAM Characterization Platform	54
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	54
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	54
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
An Octave Tuning Range and Low Phase Noise Multi-Core Mode-Switching Oscillator Using Compact Hybrid Parallel-Series Resonator	52
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	51
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	51
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	51
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	51
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	50
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	50
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	49
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	49