OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 48. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	168
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	131
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	128
IEEE Open Access Publishing	128
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	113
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	106
Welcome to a New Term in TCAS-I	104
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	97
Fast Algorithms for Resistance Distances on Signed Graphs	96
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	90
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	84
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	83
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	83
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	80
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	78
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	75
Frequency Response Model for Power Systems Including HVDC-Connected Offshore Wind Power With Communication-Free Frequency Control	74
A Handgrip-Responsive mmWave Phased Array Antenna-PA Module With Antenna-Based Capacitive Sensor for EIRP Recovery via Adaptive Current Redistribution	68
A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques	68
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	67
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	66
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	65
Guest Editorial TCAS-I Special Issue Guest Editorial Based on the 16th IEEE Latin American Symposium on Circuits and Systems	64
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	64
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	64

A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	63
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	63
An Octave Tuning Range and Low Phase Noise Multi-Core Mode-Switching Oscillator Using Compact Hybrid Parallel-Series Resonator	61
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	61
Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management	60
A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits	60
A 24.25–29.5-GHz CMOS Upconversion Transmitter With Built-In Automatic LO Feedthrough and I/Q Imbalance Calibration for 5G New Radio	60
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	59
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	58
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	57
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	55
A Compact One-Transistor-Multiple-RRAM Characterization Platform	55
An SDMT-Based CMOS Voltage Reference With a Novel NCC Scheme for PSRR Bandwidth Enhancement	54
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	54
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	53
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	53
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	51
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	50
Autaptic Self-Feedback for FPGA Realization and Real-Time Monitoring of Epileptic-Like Synchrony in Cubic–Quadratic Neuron Networks	50
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	50
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	50
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	49
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression	48
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	48
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	48