OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 49. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	186
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	173
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	147
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	145
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	131
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	131
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	128
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	100
IEEE Open Access Publishing	95
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	91
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	90
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	87
TechRxiv: Share Your Preprint Research with the World!	86
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	85
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	84
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	76
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	73
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	73
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	72
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	70
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	70
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	68
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	67
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	67
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	66

Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	65
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	64
A Compact One-Transistor-Multiple-RRAM Characterization Platform	64
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	62
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	62
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	62
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	60
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	60
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	59
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	59
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	59
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	58
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning	58
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	58
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	57
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	57
Fast Algorithms for Resistance Distances on Signed Graphs	57
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	57
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	55
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	53
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	51
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	51
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	50
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	49