OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 49. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	175
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	165
IEEE Open Access Publishing	157
TechRxiv: Share Your Preprint Research with the World!	124
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	120
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	119
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	112
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	98
Welcome to a New Term in TCAS-I	97
Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management	95
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	85
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	83
A Compact One-Transistor-Multiple-RRAM Characterization Platform	82
An Octave Tuning Range and Low Phase Noise Multi-Core Mode-Switching Oscillator Using Compact Hybrid Parallel-Series Resonator	77
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	76
Fast Algorithms for Resistance Distances on Signed Graphs	71
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	71
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	69
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	67
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	66
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	65
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	64
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	63
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	62
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	60

Setting Up the State Equations of Switched Circuits Using Homogeneous Models	59
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	59
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	59
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	57
A 24.25–29.5-GHz CMOS Upconversion Transmitter With Built-In Automatic LO Feedthrough and I/Q Imbalance Calibration for 5G New Radio	57
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	56
A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques	56
Autaptic Self-Feedback for FPGA Realization and Real-Time Monitoring of Epileptic-Like Synchrony in Cubic–Quadratic Neuron Networks	56
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	56
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	56
A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation	55
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	55
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	55
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	54
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	53
Guest Editorial TCAS-I Special Issue Guest Editorial Based on the 16th IEEE Latin American Symposium on Circuits and Systems	53
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	53
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	53
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	52
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression	52
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	52
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	51
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	51
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	50
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	49