IEEE Transactions on Circuits and Systems I-Regular Papers

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	186
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	173
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	147
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	145
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	131
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	131
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	128
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	100
IEEE Open Access Publishing	95
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	91
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	90
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	87
TechRxiv: Share Your Preprint Research with the World!	86
A Novel Design Method for CML Frequency Divider Based on C/Id and G/Id and Application for Quadrature-Injection	85
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	84
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	76
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	73
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	73
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	72
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	70
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	70
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	68
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	67
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	67
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	66

Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	65
A Compact One-Transistor-Multiple-RRAM Characterization Platform	64
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	64
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	62
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	62
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	62
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	60
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	60
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	59
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	59
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	59
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	58
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	58
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning	58
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	57
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	57
Fast Algorithms for Resistance Distances on Signed Graphs	57
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	57
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	55
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	53
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	51
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	51
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	50
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	49
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	48
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	48
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	48
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	48
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	48
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	48
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	48
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	47
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	46
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	46
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	45
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications	45
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	45
Table of Contents	45
Neuromorphic Dynamics of Chua Corsage Memristor	45
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	44
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	44
IEEE Circuits and Systems Society Information	43
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	43
Optimization of Quantum Circuits for Stabilizer Codes	43
IEEE Circuits and Systems Society Information	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	43
IEEE Circuits and Systems Society Information	43
Finite-Time Dissipative Tracking Control of Semi-Markov Jump Systems Under Multi-Channel Hybrid Attacks	42
Gain-Scheduling Fault Estimation for Discrete-Time Takagi-Sugeno Fuzzy Systems: A Depth Partitioning Approach	42

DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks	42
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density	41
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems	41
Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays	41
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games	41
Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems	41
A General Efficiency Enhancement Method for Compact Broadband Rectifiers	40
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach	40
A Switched Capacitor Modified Fibonacci Cell Used for a DC–AC Circuit Supplied by Solar Energy	39
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities	38
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory	38
Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller	38
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax	38
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs	38
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems	38
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints	38
A Triode-Based Analog Gate and Its Application in Chaotic Circuits	37
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR	37
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide	37
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-fmax Embedded Amplifier	37
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights	37
A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform	37
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation	37
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)	36
Analog Spiking Neural Network Based Phase Detector	36
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs	36
IEEE Circuits and Systems Society Information	35
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification	35
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition	35
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	35
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer	34
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation	34
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems	34
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers	34
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter	34
Homogeneous Versus Heterogeneous Graph Representation for Graph Neural Network Tasks on Electric Circuits	33
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources	33
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks	33
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation	33
Generalized Active N-Port Network Analysis for Load Modulation: Doherty Power Amplifier Incorporating Tri-Coupled-Line Combiner	33
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units	32
110–170 GHz On-Chip Calibration Using Deep Neural Networks	32
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO	32
Resilient Decentralized Frequency Regulation for Multi-Area Power Systems With Electric Vehicles Under Hybrid Cyber-Attacks	32
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration	32
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization	31
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS	31
A Novel Method for Authentication Using Chaotic Behaviour of Chua’s Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication	31
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform	31
An Energy-Efficient Capacitive-RRAM Content Addressable Memory	31
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks	31
Introducing IEEE Collabratec	30
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks	30
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K	30
A Dynamic Event-Triggered Approach to State Estimation for Switched Memristive Neural Networks With Nonhomogeneous Sojourn Probabilities	30
Table of Contents	30
A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications	30
Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference	30
Table of contents	30
Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares Method	30
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays	30
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA	30
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2023	30
IEEE Circuits and Systems Society Information	29
Entrainment of Mutually Synchronized Spatially Distributed 24 GHz Oscillators	29
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer	29
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance	28
Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range	28
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro	28
TechRxiv: Share Your Preprint Research with the World!	28
A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter	28
DetectX—Adversarial Input Detection Using Current Signatures in Memristive XBar Arrays	28
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias	28
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition	28
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications	28
Fixed-Point Kernel Adaptive Filtering for Fractional-Order Nonlinear Dynamical Systems With Applications to Chaotic Circuits	28
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation	28
A 650 kV/μs Common-Mode Resilient CMOS Galvanically Isolated Communication System	28
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms	27
Analysis and Design of Quasi-Circulating Quadrature Hybrid for Full-Duplex Wireless	27

Editorial A New Exciting Year Ahead for TCAS-I	27
IEEE Open Access Publishing	27
Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device	27
Feedback Stabilization of Switched Linear Systems: A Quantization and Triggering Joint Event-Triggered Mechanism	27
IEEE Circuits and Systems Society Information	27
Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits	27
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	27
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators	27
IEEE Circuits and Systems Society Information	26
A 36–55 V Input 0.6–2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA–5 A Load Range	26
A High-Efficiency RFEH System With Feedback-Free Fast (F3) MPPT Over a Wide Input Range	26
Semiglobal Finite-Time Stability of Impulsive Systems	26
PRADO: A Low-Latency and Energy-Efficient 6DoF Pose Refinement Accelerator With Domain-Specific Explorations	26
From Relaxation to Chaotic Oscillations: A New Paradigm for Memristor Circuits	26
Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs	26
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms	26
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria	26
Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros	25
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up	25
A 15–28 GHz Low-Noise Amplifier With 0.75-dB Gain Ripple Across the Full K-Band	25
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements	25
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN	25
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam	25
A Novel Memristive Combinational Logic for Accelerating N-bit Adders	25
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking	25
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory	25
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise	25
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault	25
A Low-Cost Digital Capacitor Current Estimation Algorithm Based on Parameter Identification for Buck Converter Application	24
A Self-Matching Rectifier Based on an Artificial Transmission Line for Enhanced Dynamic Range	24
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers	24
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture	24
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks	24
A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer	24
Data-Driven Control Algorithms for Unknown Discrete-Time Linear Periodic Systems	24
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step	24
SPP-CNN: An Efficient Framework for Network Robustness Prediction	24
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC	24
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard	24
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs	24
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance	24
Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map	23
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme	23
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax	23
A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application	23
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies	23
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems	23
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique	23
Bipartite Consensus for Quantization Communication Multi-Agents Systems With Event-Triggered Random Delayed Impulse Control	23
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line	23
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach	23
Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization	23
Table of Contents	23
Pole-Zero Cancellation Speed and Acceleration Filtering Technique With Disturbance Observer for Servo Drive Applications Without Model Parameter Information	23
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications	23
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation	22
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications	22
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems	22
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	22
Effect of Device Mismatches in Differential Oscillatory Neural Networks	22
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique	22
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis	22
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC	22
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies	22
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array	22
A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization	22
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS	22
High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller	22
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS	22
Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM	22
A 55nA Quiescent Current Power-Wise Buck Converter With 1μA–600mA Load Range and 0.5V–1.8V Flexible Output Voltage Options	22
Table of Contents	22
Guest Editorial: Special Issue Based on the 12th Edition of the Latin American Symposium on Circuits and Systems	22
Interdependence Among Voltage-Unstable Buses During Cascading Failure in Power Systems	22
Knowledge-Aided Automated Synthesis for Broadband Power Amplifier With Transformer-Coupled Resonators	21
Bidirectional High Step-Up/Down DC/DC Converter With a Coupled Inductor and Switched Capacitor	21
A 16-Channel Analog CMOS SiPM With On-Chip Front-End for D-ToF LiDAR	21
Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization	21
A Synthesis-Analysis Machine With Self-Inspection Mechanism for Automatic Design of On-Chip Inductors Based on Artificial Neural Networks	21
Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline	21
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation	21
A 9-to-42-GHz High-Gain Low-Noise Amplifier Using Coupled Interstage Feedback in 0.15-μm GaAs pHEMT Technology	21
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology	21
A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth	21
Prescribed Time Recovery From State Constraint Violation via Approximation-Free Control Approach	21
A 7.2–29.8 GHz LNA With 1.35–2.67-dB NF Using Coupled-Line-Based Transformers in 0.15-μm GaN-on-SiC Technology	21
Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits	20
A 2 MHz Bandwidth Area-Efficient Multipath Hall Sensor With a Residual Ripple of 4.1 μT	20
Joint Resource Allocation for RIS-Assisted Heterogeneous Networks With Centralized and Distributed Frameworks	20
Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking	20
Passive Post-Resonance Tuned Reflectors to Achieve Both 10-bit Phase-Shifting Resolution and Low Insertion Loss Across 20–30 GHz	20
A High-Voltage Differential SPDT T/R Switch for Ultrasound Systems	20
A Novel Adaptive Control Scheme for Automotive Electronic Throttle Based on Extremum Seeking	20
CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs	20
Huicore: A Generalized Hardware Accelerator for Complicated Functions	20