OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Transactions on Circuits and Systems I-Regular Papers is 9. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-11-01 to 2025-11-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	190
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	171
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	151
IEEE Open Access Publishing	149
TechRxiv: Share Your Preprint Research with the World!	133
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	127
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	98
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	98
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	97
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	94
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	88
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	85
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	82
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	78
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	77
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	76
A Compact One-Transistor-Multiple-RRAM Characterization Platform	74
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	71
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	70
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	68
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	66
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	66
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	64
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	63
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	62

Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	62
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	61
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	61
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	61
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	61
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	60
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	59
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	58
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	58
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	58
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	58
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	56
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	55
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	54
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	53
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	53
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	53
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	52
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	52
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	52
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	52
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	51
Fast Algorithms for Resistance Distances on Signed Graphs	50
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	49
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	49
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	49
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	48
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	48
A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation	48
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	47
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	47
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	47
Neuromorphic Dynamics of Chua Corsage Memristor	46
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	46
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	45
IEEE Circuits and Systems Society Information	44
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	44
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	44
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	44
IEEE Circuits and Systems Society Information	44
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	43
Table of Contents	43
IEEE Circuits and Systems Society Information	42
IEEE Circuits and Systems Society Information	42
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification	42
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications	42
Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares Method	41
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks	41
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K	41

Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller	40
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units	40
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints	40
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO	40
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)	39
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-f_max Embedded Amplifier	39
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide	39
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs	39
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights	39
A General Efficiency Enhancement Method for Compact Broadband Rectifiers	38
An Energy-Efficient Capacitive-RRAM Content Addressable Memory	38
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems	38
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	38
Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference	38
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	38
Homogeneous Versus Heterogeneous Graph Representation for Graph Neural Network Tasks on Electric Circuits	38
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration	37
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation	37
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform	37
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS	37
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax	37
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach	36
A Novel Method for Authentication Using Chaotic Behaviour of Chua’s Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication	36
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter	36
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems	36
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer	35
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation	35
Gain-Scheduling Fault Estimation for Discrete-Time Takagi-Sugeno Fuzzy Systems: A Depth Partitioning Approach	35
A Switched Capacitor Modified Fibonacci Cell Used for a DC–AC Circuit Supplied by Solar Energy	35
Analog Spiking Neural Network Based Phase Detector	34
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks	34
A Triode-Based Analog Gate and Its Application in Chaotic Circuits	34
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR	34
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems	34
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers	34
A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform	34
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2025	33
Resilient Decentralized Frequency Regulation for Multi-Area Power Systems With Electric Vehicles Under Hybrid Cyber-Attacks	33
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities	33
Generalized Active N-Port Network Analysis for Load Modulation: Doherty Power Amplifier Incorporating Tri-Coupled-Line Combiner	33
Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays	33
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density	33
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks	33
Finite-Time Dissipative Tracking Control of Semi-Markov Jump Systems Under Multi-Channel Hybrid Attacks	33
Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation	32
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games	32
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G_m for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs	32
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation	31
Broadband GaAs HBT Doherty Power Amplifier Using Lumped Compensation Network and Input Phase Correction for 5G Applications	31
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition	31
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA	31
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory	31
Optimization of Quantum Circuits for Stabilizer Codes	31
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks	31
Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems	31
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays	31
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization	30
110–170 GHz On-Chip Calibration Using Deep Neural Networks	30
Table of Contents	30
A Dynamic Event-Triggered Approach to State Estimation for Switched Memristive Neural Networks With Nonhomogeneous Sojourn Probabilities	30
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2023	30
A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter	30
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources	30
A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications	30
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation	30
IEEE Circuits and Systems Society Information	30
Data-Driven Control Algorithms for Unknown Discrete-Time Linear Periodic Systems	29
Pole-Zero Cancellation Speed and Acceleration Filtering Technique With Disturbance Observer for Servo Drive Applications Without Model Parameter Information	29
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	29
Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range	29
Table of Contents	29
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications	29
Introducing IEEE Collabratec	29
TechRxiv: Share Your Preprint Research with the World!	29
A Novel Memristive Combinational Logic for Accelerating N-bit Adders	28
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture	28
Analysis and Design of Quasi-Circulating Quadrature Hybrid for Full-Duplex Wireless	28
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line	28
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach	28
A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application	28

Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device	28
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs	28
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance	28
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms	28
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory	27
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up	27
Entrainment of Mutually Synchronized Spatially Distributed 24 GHz Oscillators	27
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam	27
A 15–28 GHz Low-Noise Amplifier With 0.75-dB Gain Ripple Across the Full K-Band	27
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators	27
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN	27
A 650 kV/μs Common-Mode Resilient CMOS Galvanically Isolated Communication System	27
Editorial A New Exciting Year Ahead for TCAS-I	26
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro	26
A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer	26
DetectX—Adversarial Input Detection Using Current Signatures in Memristive XBar Arrays	26
A Low-Cost Digital Capacitor Current Estimation Algorithm Based on Parameter Identification for Buck Converter Application	26
IEEE Circuits and Systems Society Information	26
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias	26
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition	26
IEEE Circuits and Systems Society Information	26
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC	26
A 36–55 V Input 0.6–2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA–5 A Load Range	26
A High-Efficiency RFEH System With Feedback-Free Fast (F³) MPPT Over a Wide Input Range	26
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax	25
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise	25
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms	25
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks	25
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems	25
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria	25
SPP-CNN: An Efficient Framework for Network Robustness Prediction	25
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer	25
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique	25
Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization	25
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault	25
Semiglobal Finite-Time Stability of Impulsive Systems	25
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies	25
A Self-Matching Rectifier Based on an Artificial Transmission Line for Enhanced Dynamic Range	25
Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map	24
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard	24
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step	24
Feedback Stabilization of Switched Linear Systems: A Quantization and Triggering Joint Event-Triggered Mechanism	24
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking	24
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers	24
Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros	24
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme	24
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements	23
PRADO: A Low-Latency and Energy-Efficient 6DoF Pose Refinement Accelerator With Domain-Specific Explorations	23
Fixed-Point Kernel Adaptive Filtering for Fractional-Order Nonlinear Dynamical Systems With Applications to Chaotic Circuits	23
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing	23
A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS	23
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems	23
Bipartite Consensus for Quantization Communication Multi-Agents Systems With Event-Triggered Random Delayed Impulse Control	23
From Relaxation to Chaotic Oscillations: A New Paradigm for Memristor Circuits	23
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance	23
Table of Contents	23
A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm	23
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces	23
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	23
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array	23
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications	23
Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs	23
Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline	23
Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization	23
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC	23
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation	22
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS	22
Guest Editorial: Special Issue Based on the 12th Edition of the Latin American Symposium on Circuits and Systems	22
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies	22
A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization	22
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology	22
Effect of Device Mismatches in Differential Oscillatory Neural Networks	22
Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits	21
Dynamic Vision With Single Photon Detectors: A Discrete DVS Architecture Using Asynchronous Sensor Front-Ends	21
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS	21
Memristor-Based Temporal Memory Neural Network Circuit Influenced by Emotional Arousal and Memory Interaction	21
A 2 MHz Bandwidth Area-Efficient Multipath Hall Sensor With a Residual Ripple of 4.1 μT	21
A 3D Waveguide Filtering Power Amplifier Characterized by Coupling Matrix With Harmonics Control Network	21
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	21
Interdependence Among Voltage-Unstable Buses During Cascading Failure in Power Systems	21
Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems	21
A Timing-Constrained Design Methodology for Radix-2^k NTT in Polynomial Arithmetic	21
PDE-Based Finite-Time Deployment of Heterogeneous Multi-Agent Systems Subject to Multiple Asynchronous Semi-Markov Chains	21
Passive Post-Resonance Tuned Reflectors to Achieve Both 10-bit Phase-Shifting Resolution and Low Insertion Loss Across 20–30 GHz	21
High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller	21
Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM	21
An E-Band Bidirectional Front-End With 20.9 dBm Peak Output Power in GaAs Process	20
A 16-Channel Analog CMOS SiPM With On-Chip Front-End for D-ToF LiDAR	20
Fully Integrated Galvanic Isolation Interface in GaN Technology	20
CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs	20
Design Flow for Hybrid CMOS/Memristor Systems—Part II: Circuit Schematics and Layout	20
Carry Disregard Approximate Multipliers	20
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application	20
A High Precision Analog Temperature Compensated Crystal Oscillator Using a New Temperature Compensated Multiplier	20
Joint Resource Allocation for RIS-Assisted Heterogeneous Networks With Centralized and Distributed Frameworks	20