IEEE Transactions on Circuits and Systems I-Regular Papers

Article	Citations
Introducing IEEE Collabratec	292
IEEE Open Access Publishing	216
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	168
IEEE Circuits and Systems Society Information	165
Improved Vector Current Control for the VSC-HVdc Converter Connected to a Very Weak AC Grid	162
IEEE Circuits and Systems Society Information	127
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	122
A Parallel Read-Write Circuit With Fast Amplitude-Adaptive Matching Scheme to Memristor Crossbar Array	119
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	116
A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference	115
Table of Contents	113
Detection and Mitigation of nBTI Aging of a High Precision Current Comparator in 16 nm FinFET Technology	112
A Wide-Range Self-Powered Current Measurement Method Based on Induced Current Multiplexing for Online Monitoring Devices in Transmission Lines	100
Analysis and Mitigation of Excess Phase Noise and Spurs in Digital-to-Time-Converter-Enhanced Fractional- N Frequency Synthesizers	97
A Novel Design Method for CML Frequency Divider Based on C/Id and G/Id and Application for Quadrature-Injection	93
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	91
Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece	88
A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler	86
IEEE Open Access Publishing	83
A Subgraph-Based Hierarchical Q-Learning Approach to Optimal Resource Scheduling for Complex Industrial Networks	81
TechRxiv: Share Your Preprint Research with the World!	80
Synthetic Diversity for Artifact Suppression and Simultaneous Multi-Band Down-Conversion in Widely-Tunable Receivers	80
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	75
Distributed Time-Varying Economic Dispatch via a Prediction-Correction Method	74
FPGA Implementation of Memristor Emulators Using Fractional Order Calculus: A High-Precision Reconfigurable Approach	74

Fast Beam Training With True-Time-Delay Arrays in Wideband Millimeter-Wave Systems	72
Three Time-Scale Singular Perturbation Hybrid Control and Large-Signal Analysis Stability in AC-Microgrids	72
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications	69
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
Table of Contents	69
TechRxiv: Share Your Preprint Research with the World!	67
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	63
IEEE Circuits and Systems Society Information	63
A Sub-1 V 90 dB-SNDR Power/BW Scalable DTDSM Using Low-Voltage Cascoded Floating Inverter Amplifiers in 130 nm CMOS	63
A Novel Single-Switch High Step-Up DC-DC Converter With High-Voltage Conversion Ratio	62
Event-Triggered Fully Distributed Bipartite Containment Control for Multi-Agent Systems Under DoS Attacks and External Disturbances	62
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	60
An 80 MS/s 70.8 dB-SNDR Radiation-Tolerant Semi-Time-Interleaved Pipelined-SAR ADC for Space Applications	59
Robot Strategy Transfer Based on Shared Feature Space for Search and Insertion Assembly	59
Adaptive Neural Control of Superheated Steam System in Ultra-Supercritical Units With Output Constraints Based on Disturbance Observer	57
LVDE: A Lightweight Threshold Voltage Distribution Estimation Strategy for High-Performance 3-D Nand Flash Memory	57
IEEE Circuits and Systems Society Information	56
TechRxiv: Share Your Preprint Research with the World!	56
Table of contents	55
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	55
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	54
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	54
IEEE Open Access Publishing	53
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	52
TechRxiv: Share Your Preprint Research with the World!	51
Table of Contents	51
IEEE Open Access Publishing	51
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	50
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	50
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	49
Table of Contents	49
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	49
Table of Contents	49
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	49
IEEE Circuits and Systems Society Information	48
TechRxiv: Share Your Preprint Research with the World!	48
A Compact Wideband SPDT Switch Using Compensating Inductors and Highpass Matching Network	47
A Ka-Band Reconfigurable Dual-Band Variable Gain Amplifier With Low Phase Variation for 5G Communications	47
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	47
Table of Contents	45
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	45
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	45
Table of Contents	45
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	44
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	43
Design and Implementation of a Dual-Mode Supercapacitor Fast Charger Employing Continuous and Fine-Tuned Pulse Currents	43
IEEE Circuits and Systems Society Information	43
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	43
Distributed Fault Detection and Dynamic Event-Triggered Consensus for Heterogeneous Multiagent Systems Under Deception Attacks	43

Inverse Proportional Chaotification Model for Image Encryption in IoT Scenarios	42
DC-Readout of Semiconductor Spin Qubits: Opportunities and Limits	42
Generating Grid Multiscroll Memristive Chua’s Circuit and Its Predefined-Time Synchronization for Secure Communication	42
Monolithic GaN-Based Multiple-Phase Bidirectional Energy Transfer With Seamless Control Applied on High-Voltage and Low-Voltage Batteries	41
Multi-Time-Scale Voltage Regulation in ADN: A Designable Event-Triggered Method	41
A 701.7 TOPS/W Compute-in-Memory Processor With Time-Domain Computing for Spiking Neural Network	41
Compact On-Chip mm-wave Reconfigurable Wideband Filtering Switch in 28-nm Bulk CMOS for Integrated Sensing and Communication System Applications	40
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	40
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	39
A Twin Circuit Theory-Based Framework for Oscillation Event Analysis in Inverter-Dominated Power Systems With Case Study for Kaua'i System	39
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation	39
Predefined-Time Precise Tracking of Uncertain MIMO Nonlinear Systems With Time-Varying Input Delay	39
Reconciliation of Statistical Approaches to Predicting Nonlinearity-Induced Spurs in Fractional-$N$ Frequency Synthesizers	38
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	38
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs	38
Table of Contents	38
Lattice Trajectory Piecewise Linear Method for the Simulation of Diode Circuits	38
An 8-bit 5-GS/s Single-Channel Hybrid ADC With a $\lambda$/4 Transmission Line Based Time Quantizer	38
A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads	38
Dual-Band Multi-Resonant Class-E Inverter With Load-Independent CC/CV Output	38
Analysis and Optimization for Voltage Overload Resilience of Hybrid Transformers Under Grid Voltage Fluctuations	38
Circuit Modeling for RRAM-Based Neuromorphic Chip Crossbar Array With and Without Write-Verify Scheme	38
Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering	38
PMU-Spill: A New Side Channel for Transient Execution Attacks	37
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS	37
An Efficient Digital Realization of Retinal Light Adaptation in Cone Photoreceptors	37
Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics	37
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	37
A Complex Band-Pass Filter for Low-Power and High-Performance Transceivers	37
Disturbance Utilization-Based Tracking Control for the Fixed-Wing UAV With Disturbance Estimation	36
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	36
Remote Robust State Estimation for Nonlinear Cyber-Physical Systems Under Denial-of-Service Attacks	36
A Memristor Emulation in 180-nm CMOS Process for Spiking Signal Generation and Chaos Application	36
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs	36
A Wireless-Powered Battery-Less Electrical Stimulator With Delay-Shift Keying (DSK) Based Downlink Data Communication	36
Design and Analysis of an On-Chip Current-Driven CMOS Parametric Frequency Divider	35
Advancing Circuit Transient Response Macromodeling: From Conventional Neural Networks to Siamese-LSTM	35
Algorithm and Architecture Design of Random Fourier Features-Based Kernel Adaptive Filters	35
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	34
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm	34
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	33
TDPRO: Time-Domain-Based Computing-in Memory Engine for Ultra-Low Power ECG Processor	33
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	33
SuperHCA: An Efficient Deep-Learning Edge Super-Resolution Accelerator With Sparsity-Aware Heterogeneous Core Architecture	33
Machine Learning Methodologies to Predict the Results of Simulation-Based Fault Injection	33
RL-Based Adaptive Optimal Bipartite Consensus Control for Nonlinear Heterogeneous MASs via Event-Triggered State Feedback	33
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs	33
Modular Modeling of Analog Organic Neuromorphic Circuits: Toward Prototyping of Hardware-Level Spiking Neural Networks	33
Analysis of Conditional Stability and Unconditional Stability and Instability for Microwave 3-Ports	33
A Comprehensive Framework for the Thévenin–Norton Theorem Using Homogeneous Circuit Models	33
Accurate Modeling of Transformer-Based Voltage-Multiplier Considering Reverse Recovery Process of the Leakage Inductance in Step-up Converter	33
A New Message Expansion Structure for Full Pipeline SHA-2	32
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT	32
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits	32
Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G	32
Design of a Quadband Doherty Power Amplifier With Large Power Back-Off Range	31
An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique	31
Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic	31
Impedance-Circuit-Based Stability Analysis for PLL-Synchronized Voltage Source Converter in Weak Grid	30
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	30
FDSOI-Based Analog Computing for Ultra-Efficient Hamming Distance Similarity Calculation	30
An Energy-Efficient CNN/Transformer Hybrid Neural Semantic Segmentation Processor With Chunk-Based Bit Plane Data Compression and Similarity-Based Token-Level Skipping Exploitation	30
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI	30
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	30
A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training	29
Fault-Tolerant Reversible-Logic Based RO-PUF for Secure Device Authentication	29
Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current	29
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks—A Concrete Threat for Masked Cryptographic Implementations	29
Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors	29
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	29
Hybrid-Bridge-Based Dual-Active-Bridge Converter With an Asymmetric Active-Neutral-Point-Clamped Three-Level Bridge	29
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces	29
A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications	29
LMI-Based Robust Stability Analysis of Discrete-Time Fractional-Order Systems With Interval Uncertainties	28
On Synchronization Design and State Observer Design of (Singular) Boolean Networks	28
On the Resilience Analysis of DC Microgrids With Power Buffer Control	28
Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas	28
A 95.2% Efficiency DC–DC Boost Converter Using Peak Current Fast Feedback Control (PFFC) for Improved Load Transient Response	28
LMI Stability Condition for Delta Fractional Order Systems With Region Approximation	28
Facilitating and Determining Turing Patterns in 3-D Memristor Cellular Neural Networks	28

Mittag-Leffler Stability of Fractional-Order Nonlinear Differential Systems With State-Dependent Delays	27
A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS	27
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	27
T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure	27
A Chopper-Stabilized Switched-Capacitor Front-End for Peripheral Nervous System Recording	27
Ternary LDPC Error Correction for Arrhythmia Classification in Wireless Wearable Electrocardiogram Sensors	27
A 6.78 MHz Single-Stage Wireless Power Transmitter Using a 3-Mode Zero-Voltage Switching Class-D PA	27
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution	27
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications	27
A Fully Integrated Low-Power Hall-Based Isolation Amplifier With IMR Greater Than 120 dB	27
Finite-Time State Zonotopes Design for Asynchronously Switched Systems With Application to a Switched Converter	27
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	26
Active Charge Balancer With Adaptive 3.3 V to 38 V Supply Compliance for Neural Stimulators	26
Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array	26
Extended Dissipative Scalable Control for AC Islanded Microgrids	26
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	26
Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing	26
A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD	26
A New Adaptive Sparse Pseudospectral Approximation Method and its Application for Stochastic Power Flow	26
Self-Synchronized DS/SS With High Spread Factors for Robust Millimeter-Wave Datalinks	26
A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme	26
Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers	26
A 2.4–6 GHz Broadband GaN Power Amplifier for 802.11ax Application	26
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network	25
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme	25
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation	25
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	25
The Dickson Charge Pump as a Signal Amplifier	25
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm	25
ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification	25
Improved Fixed-Time Stability Lemma of Discontinuous System and its Application	25
A Transistor-Based High-Efficiency Rectifier Using Input Second Harmonic Component	24
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications	24
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	24
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	24
Construction and Application of a Neuromorphic Circuit With Excitatory and Inhibitory Post-Synaptic Conduction Channels Implemented Using Dual-Gate Thin-Film Transistors	24
Motion Detection and Analysis Using Multimaterial Fiber Sensors	24
Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs	24
A Coupling Matrix Synthesized Three-Dimensional Filtering Power Amplifier	24
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System	24
A 1.8–5.4-GHz GaN MMIC Distributed Efficient Power Amplifier With Reactance Compensation and Adaptive Biasing	24
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	24
A CMOS Energy Harvesting Interface Circuit With Cycle-to-Cycle Frequency-to-Amplitude Conversion MPPT for Centimeter-Scale Wind Turbine	23
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier	23
Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks	23
0.35-V SR-Enhanced Bulk-Driven OTA for Loads up to 10 nF	23
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output	23
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs	23
Buck Circuit Design With Pseudo-Constant Frequency and Constant On-Time for High Current Point-of-Load Regulation	23
Sampled-Hold-Based Consensus Control for Second-Order Multiagent Systems Under Aperiodically Intermittent Communication	23
Stability of Logical Dynamic Systems With a Class of Constrained Switching	23
Model Order Reduction for Delayed PEEC Models With Guaranteed Accuracy and Observed Stability	23
A 36 μW 2.8–3.4 dB Noise Figure Impedance Boosted and Noise Attenuated LNA for NB-IoT	23
A Cycle by Cycle FSK Demodulator With High Sensitivity of 1% Frequency Modulation Index for Implantable Medical Devices	23
Synchronization on Directed Delayed Duplex Networks: From the Perspective of Coupled Delays	23
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators	23
A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR	22
CAMiSE: Content Addressable Memory-Integrated Searchable Encryption	22
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	22
A Review of Sub- μ W CMOS Analog Computing Circuits for Instant 1-Dimensional Audio Signal Processing in Always-On Edge Devices	22
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	22
Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application	22
Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications	22
A MEMS-CMOS Microsystem for Contact-Less Temperature Measurements	22
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling	21
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating	21
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	21
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM	21
Balanced-to-Unbalanced Quadrature Couplers With Wide-Band Common-Mode Suppression	21
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network	21
Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination	21
A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network	21
Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit	21
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting	21
A Wide Tracking Range Heterodyne Phase-Tracking Receiver With 1-bit Phase-Domain Demodulation	21
Load Frequency Control of Power Systems With Multiple Transmission Delays Under Aperiodic Sampled-Data	21
An Efficient Three-Phase Soft-Switching Inverter With Simplified Asymmetric Single Auxiliary Circuit on Each Bridge Arm for Low-Speed AC Motor Drive	21
Balanced Filtering Phase Shifters With Low Phase Deviation and High Common-Mode Suppression	21
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication	21
A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver	21
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	21
Offset Boosting-Oriented Construction of Multi-Scroll Attractor via a Memristor Model	21
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture	21
Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array	21
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	21
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	20
Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network	20
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	20
An 11 pJ/Bit Multichannel OOK/FSK/QPSK Transmitter With Multi-Phase Injection-Locking and Frequency Multiplication Techniques	20
Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors	20
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	20
A 1.01 NEF Low-Noise Amplifier Using Complementary Parametric Amplification	20
Neuromorphic Dynamics of Chua Corsage Memristor	20
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop	20
Memristor Crossbar Arrays Performing Quantum Algorithms	20