OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Computer Architecture Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
Toward Practical 128-Bit General Purpose Microarchitectures	112
Characterization and Analysis of Text-to-Image Diffusion Models	37
Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory	27
Old is Gold: Optimizing Single-Threaded Applications With ExGen-Malloc	25
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture	23
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit	22
NeuroMTA: Programmable Simulation Framework for Multi-Tile NPU Architectures	19
The Architectural Sustainability Indicator	15
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication	13
Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure	12
De-Quantization Penalties for Interactive LLM Inference on Prosumer GPUs	12
Context-Aware Set Dueling for Dynamic Policy Arbitration	12
MoSKA: Mixture of Shared KV Attention for Efficient Long-Sequence LLM Inference	11
A Quantitative Analysis of Mamba-2-Based Large Language Model: Study of State Space Duality	11
In-Depth Characterization of Machine Learning on an Optimized Multi-Party Computing Library	10
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems	9
Time Series Machine Learning Models for Precise SSD Access Latency Prediction	9
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	9
SoCurity: A Design Approach for Enhancing SoC Security	9
AiDE: Attention-FFN Disaggregated Execution for Cost-Effective LLM Decoding on CXL-PNM	8
Exploring KV Cache Quantization in Multimodal Large Language Model Inference	8
Wafer-Scale GPU Memory Pool With In-Package Optics for Enhanced Capacity and Bandwidth	8
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	7
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs	7
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing	7

A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	7
In-Memory Versioning (IMV)	7
REDIT: Redirection-Enabled Memory-Side Directory Architecture for CXL Memory Fabric	7
Disaggregated Speculative Decoding for Carbon-Efficient LLM Serving	6
Reducing Metadata and Page Migration Overheads in CXL-Based Secure Tiered Memory	6
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring	6
Thread-Adaptive: High-Throughput Parallel Architectures of SLH-DSA on GPUs	6
Exploring the DIMM PIM Architecture for Accelerating Time Series Analysis	6
StreamDQ: HBM-Integrated On-the-Fly DeQuantization via Memory Load for Large Language Models	6
High-Bandwidth Flash for KV Caches: Endurance and Performance Implications	6
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture	6
Enabling Computation and Communication Overlap in PIMs for On-Device LLM Inference	6
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference	6
Improving Performance on Tiered Memory With Semantic Data Placement	6
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	6
NoHammer: Preventing Row Hammer With Last-Level Cache Management	5
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	5
Hardware-Accelerated Parallel Wrong-Path Execution for Spectre Gadget Detection	5
PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM	5
Nighthawk: Zero-Copy Cache Quarantine for Invisible Speculation	4
pNet-gem5: Full-System Simulation With High-Performance Networking Enabled by Parallel Network Packet Processing	4
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information	4
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	4
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	4
ReplayOpt: Optimizer-State Replay to Resolve Critical-Path Bottlenecks in Offloaded Training	4
RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience	4
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network	4
Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology	4
Xami : E x pert-Aware A daptive Compression for Mi	3
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs	3
Hisui: Unlocking Tiered Memory Efficiency for FaaS Workloads	3
SSD Offloading for LLM Mixture-of-Experts Weights Considered Harmful in Energy Efficiency	3
Camulator: A Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs	3
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications	3
A Quantum Computer Trusted Execution Environment	3
Guard Cache: Creating Noisy Side-Channels	3
Enabling Cost-Efficient LLM Inference on Mid-Tier GPUs With NMP DIMMs	3
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	3
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	3
KiF: Accelerating Low-Batch LLM Inference Using In-Flash KV Cache	3
Memory-Centric MCM-GPU Architecture	3
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	3
Energy-Efficient Bayesian Inference Using Bitstream Computing	3
Fast Performance Prediction for Efficient Distributed DNN Training	3
LeakDiT: Diffusion Transformers for Trace-Augmented Side-Channel Analysis	3
Driving the Core Frontend With LiteBTB	3
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems	3
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	3
Agentic LLMs for Microarchitecture Research: The Role of the Human Architect	3
H ³ : H ybrid Architecture Using H igh Bandwidth Memory	3

Understanding the Performance Behaviors of End-to-End Protein Design Pipelines on GPUs	3
SoftmaxPIM: An HBM-Based PIM Architecture for Accelerating GeMV–Softmax Execution Pipeline	3
NDPool: Correctness-Preserving Shared Execution for Efficient LLM Inference on CXL-NDP Systems	3
Fast Inter-Enclave Communication Encryption	3
Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads	2
LWAL: Lightweight Adaptive Learning-Driven Cache Bypassing for GPUs	2
CABANA : Cluster-Aware Query Batching for Accelerating Billion-Scale ANNS With Intel AMX	2
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture	2
Redundant Array of Independent Memory Devices	2
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks	2
Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System	2
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	2
3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving	2
Accelerating Page Migrations in Operating Systems With Intel DSA	2
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs	2
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	2
Direct-Coding DNA With Multilevel Parallelism	2
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	2
EgDiff: An Enhanced Global Load Value Predictor	2
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI	2
Amethyst: Reducing Data Center Emissions With Dynamic Autotuning and VM Management	2
MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage	2
On the Feasibility Boundaries of LLM Prefill Inference on Unified-Memory Edge SoCs	2
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	2
Exploring High-Bandwidth Flash for Modern LLM Inference: Opportunities and Challenges	2
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors	2
Near-HBM Tensor Core Acceleration for Fine-Grained Sparse Matrix-Matrix Multiplication	2
Architectural Implications of GNN Aggregation Programming Abstractions	2
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	2
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	2
Cost-Effective Extension of DRAM-PIM for Group-Wise LLM Quantization	2
Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads	2
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs	2
On Internally Tagged Instruction Set Architectures	2
Minimal Counters, Maximum Insight: Simplifying System Performance With HPC Clusters for Optimized Monitoring	2
CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads	1
Efficient MoE Model Fine-Tuning on Commodity GPU Server With Offloading	1
MajorK: Majority Based kmer Matching in Commodity DRAM	1
X-PPR: Post Package Repair for CXL Memory	1
Fusing Adds and Shifts for Efficient Dot Products	1
A Case for Hardware Memoization in Server CPUs	1
Clover: Storage-Efficient Page Table Replication in Wafer-Scale GPUs	1
Tulip: Turn-Free Low-Power Network-on-Chip	1
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks	1
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs	1
HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation	1
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator	1
BlockPIM: Enabling Sparse LLM Inference on Dense PIM Architectures	1
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models	1
An Intermediate Language for General Sparse Format Customization	1
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	1
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models	1
Privilege Level Dynamics and Their Impact on Conditional Branch Prediction Performance in FaaS	1
Architectural Security Regulation	1
SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack	1
GPU-Centric Memory Tiering for LLM Serving With NVIDIA Grace Hopper Superchip	1
Contention-Aware GPU Thread Block Scheduler for Efficient GPU-SSD	1
A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency	1
Exploiting Intel AMX Power Gating	1
InfAMAX: Bridging the Compute-Memory Gap in Intel AMX for Efficient LLM Inference	1
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices	1
TeleVM: A Lightweight Virtual Machine for RISC-V Architecture	1
Capacity-Latency Tradeoffs in CXL Memory Expander at Hyperscale	1
MixDiT: Accelerating Image Diffusion Transformer Inference With Mixed-Precision MX Quantization	1
Halis: A Hardware-Software Co-Designed Near-Cache Accelerator for Graph Pattern Mining	1
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline	1
Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory	1
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management	1
Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow	1
Intelligent SSD Firmware for Zero-Overhead Journaling	1
Cache and Near-Data Co-Design for Chiplets	1
Dicemite: Scaling Shared-Memory Isolation for Highly Consolidated FaaS Workers	1
Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines	1
Exploiting Direct Memory Operands in GPU Instructions	1
Low-Latency PIM Accelerator for Edge LLM Inference	1
A Partial Tag–Data Decoupled Architecture for Last-Level Cache Optimization	1
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays	1
GEMM the New Gem: The Inevitable Kernel and its Sensitivity to Compiler Optimizations and Libraries	1