OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Computer Architecture Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)

Article	Citations
Learned Performance Model for SSD	30
Speculative Multi-Level Access in LSM Tree-Based KV Store	29
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture	17
Characterization and Analysis of Text-to-Image Diffusion Models	13
Toward Practical 128-Bit General Purpose Microarchitectures	12
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit	12
2021 Index IEEE Computer Architecture Letters Vol. 20	11
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication	11
Scale-Model Simulation	11
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD	11
SoCurity: A Design Approach for Enhancing SoC Security	10
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs	10
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems	10
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	10
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	9
In-Memory Versioning (IMV)	9
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions	8
Exploring the DIMM PIM Architecture for Accelerating Time Series Analysis	8
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	8
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing	8
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference	7
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture	7
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring	7
NoHammer: Preventing Row Hammer With Last-Level Cache Management	6
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	6

Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	6
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	5
Memory-Centric MCM-GPU Architecture	5
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	5
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training	5
Managing Prefetchers With Deep Reinforcement Learning	5
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network	5
Data-Aware Compression of Neural Networks	5
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information	5
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	4
Guard Cache: Creating Noisy Side-Channels	4
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	4
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs	4
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	4
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics	4
Chopping off the Tail: Bounded Non-Determinism for Real-Time Accelerators	4
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems	4
Fast Performance Prediction for Efficient Distributed DNN Training	4
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	4
Architectural Implications of GNN Aggregation Programming Abstractions	3
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	3
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	3
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs	3
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications	3
Direct-Coding DNA With Multilevel Parallelism	3
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	3
Accelerators & Security: The Socket Approach	3
A Quantum Computer Trusted Execution Environment	3
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	3
HBM3 RAS: Enhancing Resilience at Scale	2
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	2
Accelerating Page Migrations in Operating Systems With Intel DSA	2
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	2
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors	2
Redundant Array of Independent Memory Devices	2
Cost-Effective Extension of DRAM-PIM for Group-Wise LLM Quantization	2
Halis: A Hardware-Software Co-designed Near-Cache Accelerator for Graph Pattern Mining	2
Amethyst: Reducing Data Center Emissions With Dynamic Autotuning and VM Management	2
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	2
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs	2
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	2
A First-Order Model to Assess Computer Architecture Sustainability	2
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	2
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI	2
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline	2
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models	2
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture	2
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks	2

IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs	2
Energy-Efficient Bayesian Inference Using Bitstream Computing	2
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	2
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	2
Minimal Counters, Maximum Insight: Simplifying System Performance With HPC Clusters for Optimized Monitoring	2
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	2
MQSim-E: An Enterprise SSD Simulator	1
Characterizing and Understanding HGNNs on GPUs	1
GPU-Centric Memory Tiering for LLM Serving With NVIDIA Grace Hopper Superchip	1
An Intermediate Language for General Sparse Format Customization	1
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models	1
Architectural Security Regulation	1
A Case for Hardware Memoization in Server CPUs	1
SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack	1
Hashing ATD Tags for Low-Overhead Safe Contention Monitoring	1
GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks	1
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs	1
Exploiting Intel AMX Power Gating	1
Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory	1
MajorK: Majority Based kmer Matching in Commodity DRAM	1
MixDiT: Accelerating Image Diffusion Transformer Inference With Mixed-Precision MX Quantization	1
LSim: Fine-Grained Simulation Framework for Large-Scale Performance Evaluation	1
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays	1
Modeling Periodic Energy-Harvesting Computing Systems	1
TeleVM: A Lightweight Virtual Machine for RISC-V Architecture	1
Intelligent SSD Firmware for Zero-Overhead Journaling	1
Structured Combinators for Efficient Graph Reduction	1
Tulip: Turn-Free Low-Power Network-on-Chip	1
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks	1
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices	1
Characterizing and Understanding Distributed GNN Training on GPUs	1
Approximate SFQ-based Computing Architecture Modeling with Device-level Guidelines	1
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications	1
X-PPR: Post Package Repair for CXL Memory	1
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs	1
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator	1
On Variable Strength Quantum ECC	1
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management	1
Exploiting Direct Memory Operands in GPU Instructions	1