OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Computer Architecture Letters is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)

Article	Citations
Speculative Multi-Level Access in LSM Tree-Based KV Store	37
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture	32
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit	15
Characterization and Analysis of Text-to-Image Diffusion Models	15
The Architectural Sustainability Indicator	15
Old is Gold: Optimizing Single-Threaded Applications With ExGen-Malloc	13
Toward Practical 128-Bit General Purpose Microarchitectures	13
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication	12
Time Series Machine Learning Models for Precise SSD Access Latency Prediction	11
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs	10
SoCurity: A Design Approach for Enhancing SoC Security	10
2021 Index IEEE Computer Architecture Letters Vol. 20	10
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	9
In-Memory Versioning (IMV)	8
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	8
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	8
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems	8
Exploring the DIMM PIM Architecture for Accelerating Time Series Analysis	7
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring	7
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing	7
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference	7
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture	6
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	6
PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM	6
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	6

Managing Prefetchers With Deep Reinforcement Learning	5
pNet-gem5: Full-System Simulation With High-Performance Networking Enabled by Parallel Network Packet Processing	5
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information	5
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network	5
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	5
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	5
NoHammer: Preventing Row Hammer With Last-Level Cache Management	5
Memory-Centric MCM-GPU Architecture	4
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
SSD Offloading for LLM Mixture-of-Experts Weights Considered Harmful in Energy Efficiency	4
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	4
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	4
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	4
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems	4
Architectural Implications of GNN Aggregation Programming Abstractions	3
Accelerators & Security: The Socket Approach	3
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	3
Camulator: a Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs	3
Direct-Coding DNA With Multilevel Parallelism	3
Fast Performance Prediction for Efficient Distributed DNN Training	3
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications	3
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	3
A Quantum Computer Trusted Execution Environment	3
Guard Cache: Creating Noisy Side-Channels	3
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	3
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors	2
A First-Order Model to Assess Computer Architecture Sustainability	2
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	2
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs	2
Accelerating Page Migrations in Operating Systems With Intel DSA	2
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks	2
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs	2
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	2
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	2
Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads	2
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs	2
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	2
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	2
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	2
Energy-Efficient Bayesian Inference Using Bitstream Computing	2
Minimal Counters, Maximum Insight: Simplifying System Performance With HPC Clusters for Optimized Monitoring	2
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	2
EgDiff: An Enhanced Global Load Value Predictor	2