OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Computer Architecture Letters is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator	103
SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD	40
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization	29
GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers	28
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning	24
The Entangling Instruction Prefetcher	17
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator	17
MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator	15
Rebasing Instruction Prefetching: An Industry Perspective	13
A Cross-Stack Approach Towards Defending Against Cryptojacking	13
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators	12
HBM3 RAS: Enhancing Resilience at Scale	11
Cryogenic PIM: Challenges & Opportunities	9
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles	8
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators	8
TRiM: Tensor Reduction in Memory	8
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions	8
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs	7
A Day In the Life of a Quantum Error	7
BTB-X: A Storage-Effective BTB Organization	7
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	6
Harnessing Pairwise-Correlating Data Prefetching With Runahead Metadata	6
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	6
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training	6
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores	6

MCsim: An Extensible DRAM Memory Controller Simulator	6
A Lightweight Memory Access Pattern Obfuscation Framework for NVM	5
Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs	5
Deep Partitioned Training From Near-Storage Computing to DNN Accelerators	5
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	5
Instruction Criticality Based Energy-Efficient Hardware Data Prefetching	5
LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking	5
GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks	5
A First-Order Model to Assess Computer Architecture Sustainability	4
WPC: Whole-Picture Workload Characterization Across Intermediate Representation, ISA, and Microarchitecture	4
Zero-Copying I/O Stack for Low-Latency SSDs	4
Hardware Acceleration for GCNs via Bidirectional Fusion	4
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
Characterizing and Understanding HGNNs on GPUs	4
Managing Prefetchers With Deep Reinforcement Learning	4
Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure	4
Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms	4
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD	4
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	3
PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures	3
Infinity Stream: Enabling Transparent and Automated In-Memory Computing	3
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	3
Near-Data Processing in Memory Expander for DNN Acceleration on GPUs	3
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs	3
Characterizing and Understanding Distributed GNN Training on GPUs	3
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching	3
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	3
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing	3
Data-Aware Compression of Neural Networks	3