IET Circuits Devices & Systems

Papers
(The TQCC of IET Circuits Devices & Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)
ArticleCitations
Design of ternary logic gates and circuits using GNRFETs28
Design and applications of interval observers for uncertain dynamical systems23
Design of 10T SRAM cell with improved read performance and expanded write margin22
A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage20
A high‐performance full swing 1‐bit hybrid full adder cell19
New mixed‐mode second‐generation voltage conveyor based first‐order all‐pass filter17
Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction17
A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters15
A new coplanar design of a 4‐bit ripple carry adder based on quantum‐dot cellular automata technology15
An effective nano design of demultiplexer architecture based on coplanar quantum‐dot cellular automata15
Floating memristor and inverse memristor emulation configurations with electronic/resistance controllability14
Memristor‐based stateful logic gates for multi‐functional logic circuit14
A simple memristive jerk system13
Developed wireless sensor network to supervise the essential parameters in greenhouses for internet of things applications13
Split gated silicon nanotube FET for bio‐sensing applications13
Single DDCC− based simulated floating inductors and their applications12
Single and double‐gate based AlGaN/GaN MOS‐HEMTs for the design of low‐noise amplifiers: a comparative study11
Dual‐band CPW rectenna for low input power energy harvesting applications10
Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system10
Comprehensive review of nonisolated bridgeless power factor converter topologies10
Field Programmable Gate Array based elliptic curve Menezes‐Qu‐Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives10
Fast signed multiplier using Vedic Nikhilam algorithm9
3D‐IC partitioning method based on genetic algorithm9
Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell9
Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization8
Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications8
Design of a voltage‐programmed V TH compensating pixel circuit for AMOLED displays using diode‐connected a‐IGZO TFT8
A 1–5 GHz 22 mW receiver frontend with active‐feedback baseband and voltage‐commutating mixers in 65 nm CMOS7
FPGA and ASIC realisation of EMD algorithm for real‐time signal processing7
Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual‐material gate‐oxide‐stack double‐gate TFET7
Reduced complexity hard‐ and soft‐input BCH decoding with applications in concatenated codes7
Area–delay and energy efficient multi‐operand binary tree adder7
Analytical modelling of tantalum/titanium oxide‐based multi‐layer selector to eliminate sneak path current in RRAM arrays7
Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application7
A novel buffering fault‐tolerance approach for network on chip (NoC)7
Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit7
Ultrawideband LNA 1960–2019: Review6
CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance6
Design and realisation of a fractional‐order sinusoidal oscillator6
A high speed processor for elliptic curve cryptography over NIST prime field6
Fully implantable, multi‐channel microstimulator with tracking supply ribbon, multi‐output charge pump and energy recovery6
Comprehensive survey of ternary full adders: Statistics, corrections, and assessments6
Spice modelling of a tri‐state memristor and analysis of its series and parallel characteristics6
Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit6
MPPT integrated DC–DC boost converter for RF energy harvester6
Performance analysis of mixed CNT bundle interconnects at 10 nm technology6
Fast‐locking PLL based on a novel PFD‐CP structure and reconfigurable loop filter6
Practical test method for the sensitivity of programmable logic controller to voltage sags and short interruptions5
Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array5
Rail‐to‐rail complementary input StrongARM comparator for low‐power applications5
Pinched hysteresis loops in non‐linear resonators5
Audio classification using grasshopper‐ride optimization algorithm‐based support vector machine5
Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems5
Design of narrow transition band variable bandwidth digital filter5
Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET5
Current‐voltage model of a graphene nanoribbon p‐n junction and Schottky junction diode5
FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing5
High gain operational amplifier and a comparator with a‐IGZO TFTs5
Low storage power and high noise margin ternary memory cells in nanoelectronics5
An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation5
Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing5
A hybrid attack detection strategy for cybersecurity using moth elephant herding optimisation‐based stacked autoencoder4
Dual feedback IRC ring for chaotic waveform generation4
Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation4
Hall‐effect sensors based on AlGaN/GaN heterojunctions on Si substrates for a wide temperature range4
Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit4
Recent trends towards privacy‐preservation in Internet of Things, its challenges and future directions4
New full‐wave rectifier based on modified voltage differencing transconductance amplifier4
A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process4
Compact wide stopband microstrip diplexer with flat channels for WiMAX and wireless applications4
Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision4
A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications4
Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell4
New method of finding exact frequency response for feedback amplifiers4
Fast automated on‐chip artefact removal of EEG for seizure detection based on ICA‐R algorithm and wavelet denoising4
A high‐capacity and nonvolatile spintronic associative memory hardware accelerator4
Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator4
Four‐stage CMOS amplifier: frequency compensated using differential block4
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