IET Computers and Digital Techniques

Papers
(The median citation count of IET Computers and Digital Techniques is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)
ArticleCitations
A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment10
7
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems6
An embedded intelligence engine for driver drowsiness detection5
Q‐scheduler: A temperature and energy‐aware deep Q‐learning technique to schedule tasks in real‐time multiprocessor embedded systems5
Guest Editorial: Special issue on battery‐free computing5
5
E‐Commerce Logistics Software Package Tracking and Route Planning and Optimization System of Embedded Technology Based on the Intelligent Era5
A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms4
Design and analysis of a novel fast adder using logical effort method3
Machine learning guided thermal management of Open Computing Language applications on CPU‐GPU based embedded platforms3
A Configurable Accelerator for CNN‐Based Remote Sensing Object Detection on FPGAs3
EmRep: Energy management relying on state‐of‐charge extrema prediction3
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine3
An Efficient RTL Design for a Wearable Brain–Computer Interface3
Efficient implementation of low cost and secure framework with firmware updates3
TLP: Towards three‐level loop parallelisation3
Research on mapping recognition of arc welding molten pool characterisation and penetration state based on embedded system2
ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints2
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters2
2
Fast approximation of the top‐k items in data streams using FPGAs2
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits2
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture2
Energy‐Efficient Branch Predictor via Instruction Block Type Prediction in Decoupled Frontend2
A Reconfigurable Coarse‐to‐Fine Approach for the Execution of CNN Inference Models in Low‐Power Edge Devices2
Hybrid multi‐level hardware Trojan detection platform for gate‐level netlists based on XGBoost1
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling1
Application of Lightweight Target Detection Algorithm Based on YOLOv8 for Police Intelligent Moving Targets1
A Fast Fully Parallel Ant Colony Optimization Algorithm Based on CUDA for Solving TSP1
1
Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists1
Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow1
Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP1
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