ACM Transactions on Reconfigurable Technology and Systems

Papers
(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)
ArticleCitations
Design and Evaluation of a Tunable PUF Architecture for FPGAs102
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators94
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination31
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain29
Mitigating Voltage Attacks in Multi-Tenant FPGAs27
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities25
Tensor Slices: FPGA Building Blocks For The Deep Learning Era24
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression24
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme22
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E222
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application20
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge19
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR16
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost16
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism16
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs14
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching14
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis13
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration13
Accelerating In-memory Database Functionality with FPGAs13
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators13
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks12
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs12
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS12
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator12
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains11
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow11
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures11
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization10
Cloud Building Block Chip for Creating FPGA and ASIC Clouds10
Covert-channels in FPGA-enabled SmartSSDs9
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs9
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs8
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters8
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units8
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs8
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs8
Introduction to the Special Section on FPL 20197
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric7
Introduction to Special Issue on FPGAs in Data Centers7
An FPGA Accelerator for Genome Variant Calling7
QUEKUF: an FPGA Union Find Decoder for Quantum Error Correction on the Toric Code6
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference6
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns6
High-efficiency Compressor Trees for Latest AMD FPGAs6
Compressing Neural Networks using Learnable 1D Non-Linear Functions5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
xDNN: Inference for Deep Convolutional Neural Networks5
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP5
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices5
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator5
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
Introduction to the Special Section on FCCM 20225
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher5
Strega : An HTTP Server for FPGAs5
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
Introduction to the Special Section on FPL 20204
Introduction to Special Issue on FPGAs in Data Centers, Part II4
Data and Computation Reuse in CNNs Using Memristor TCAMs4
Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications4
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs4
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems4
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis4
The Impact of Terrestrial Radiation on FPGAs in Data Centers4
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing4
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition4
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking4
CSAIL2019 Crypto-Puzzle Solver Architecture4
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA4
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector4
Voltage Sensor Implementations for Remote Power Attacks on FPGAs4
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs3
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators3
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning3
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms3
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures3
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design3
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication3
Hipernetch: High-Performance FPGA Network Switch3
A Computation of the Ninth Dedekind Number Using FPGA Supercomputing3
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation3
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms3
Introduction to the Special Issue on FPT 20213
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track3
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy3
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design3
Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis3
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster3
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing3
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform3
NAPOLY: A Non-deterministic Automata Processor OverLaY3
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge2
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations2
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators2
Introduction to Special Section on FPGA 20202
Practical Model Checking on FPGAs2
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators2
Introduction to the Special Issue on FPL 20222
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree2
Resource Sharing in Dataflow Circuits2
Improving Loop Parallelization by a Combination of Static and Dynamic Analyses in HLS2
The Future of FPGA Acceleration in Datacenters and the Cloud2
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model2
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration2
DFlows : A Flow-based Programming Approach for a Polyglot Design-Space Exploration Framework2
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines2
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design2
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications2
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S2
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration2
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data2
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s2
Introduction to Special Section on FPGA 20212
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining2
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