ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)
ArticleCitations
Multi-Tenant Cloud FPGA: A Survey on Security, Trust and Privacy94
Introduction to Special Section on FPGA 202186
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack29
Introduction to the Special Section on FPL 201928
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC26
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators20
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination20
Adaptive Clock Management of HLS-generated Circuits on FPGAs19
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs18
Median Filters on FPGAs for Infinite Data and Large, Rectangular Windows16
Design and Evaluation of a Tunable PUF Architecture for FPGAs15
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud14
Introduction to Special Issue on FPGAs in Data Centers14
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric13
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns12
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis12
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation12
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track11
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration11
Introduction to the Special Section on FPGA 202211
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators11
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s11
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining11
An FPGA Accelerator for Genome Variant Calling10
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform10
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design9
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model9
High-efficiency Compressor Trees for Latest AMD FPGAs9
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain8
AxOMaP : Designing FPGA-based A ppro x imate Arithmetic O perators using 8
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities7
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference7
Tensor Slices: FPGA Building Blocks For The Deep Learning Era7
Mitigating Voltage Attacks in Multi-Tenant FPGAs7
FPGA HLS Today: Successes, Challenges, and Opportunities7
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication7
High-throughput TRNG design with novelty adjustable TDC based on STR6
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads6
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design6
Practical Model Checking on FPGAs5
Hipernetch: High-Performance FPGA Network Switch5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
xDNN: Inference for Deep Convolutional Neural Networks5
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?5
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator5
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning5
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme5
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling5
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression5
A Survey on FPGA Cybersecurity Design Strategies5
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network5
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure5
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster4
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow4
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip4
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs4
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits4
Topgun: An ECC Accelerator for Private Set Intersection4
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E24
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP4
Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors4
Strega : An HTTP Server for FPGAs4
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration4
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism4
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