ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 5. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)
ArticleCitations
Design and Evaluation of a Tunable PUF Architecture for FPGAs102
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators94
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination31
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain29
Mitigating Voltage Attacks in Multi-Tenant FPGAs27
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities25
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression24
Tensor Slices: FPGA Building Blocks For The Deep Learning Era24
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme22
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E222
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application20
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge19
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism16
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR16
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost16
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching14
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs14
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators13
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis13
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration13
Accelerating In-memory Database Functionality with FPGAs13
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs12
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS12
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator12
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks12
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow11
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures11
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains11
Cloud Building Block Chip for Creating FPGA and ASIC Clouds10
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization10
Covert-channels in FPGA-enabled SmartSSDs9
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs9
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs8
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs8
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters8
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units8
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs8
Introduction to Special Issue on FPGAs in Data Centers7
An FPGA Accelerator for Genome Variant Calling7
Introduction to the Special Section on FPL 20197
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric7
High-efficiency Compressor Trees for Latest AMD FPGAs6
QUEKUF: an FPGA Union Find Decoder for Quantum Error Correction on the Toric Code6
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference6
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns6
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
Introduction to the Special Section on FCCM 20225
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher5
Strega : An HTTP Server for FPGAs5
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
Compressing Neural Networks using Learnable 1D Non-Linear Functions5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
xDNN: Inference for Deep Convolutional Neural Networks5
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP5
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices5
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator5
0.36791396141052