OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)

Article	Citations
VTR 8	159
FPGAD efender	57
The Future of FPGA Acceleration in Datacenters and the Cloud	54
FPGA HLS Today: Successes, Challenges, and Opportunities	46
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme	21
FPGA Logic Block Architectures for Efficient Deep Learning Inference	20
FOS	20
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects	17
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration	16
MEG	16
Mitigating Voltage Attacks in Multi-Tenant FPGAs	14
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization	12
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components	11
An Optimized GIB Routing Architecture with Bent Wires for FPGA	10
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems	10
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA	10
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning	10
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs	9
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator	8
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure	8
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD	8
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling	7
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs	7
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications	7
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs	7

Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations	7
Voltage Sensor Implementations for Remote Power Attacks on FPGAs	7
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters	6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric	6
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations	6
xDNN: Inference for Deep Convolutional Neural Networks	6
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS	6
Tensor Slices: FPGA Building Blocks For The Deep Learning Era	6
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement	5
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis	5
Design of Distributed Reconfigurable Robotics Systems with ReconROS	5
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures	5
UNILOGIC	5
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs	4
Model-based Design of Hardware SC Polar Decoders for FPGAs	4
Stratix 10 NX Architecture	4
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding	4
A Survey on FPGA Cybersecurity Design Strategies	4
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud	4
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM	4
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium	4
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs	4
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology	4
Specializing FGPU for Persistent Deep Learning	4
Approaches for FPGA Design Assurance	4
FPGA Architecture Exploration for DNN Acceleration	4
Parallel Unary Computing Based on Function Derivatives	4
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography	4