ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 5. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)
ArticleCitations
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities120
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination103
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain35
Design and Evaluation of a Tunable PUF Architecture for FPGAs31
Tensor Slices: FPGA Building Blocks For The Deep Learning Era29
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators29
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models28
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E225
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism23
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge21
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application20
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR19
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost17
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression16
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching15
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs14
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators14
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis14
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration13
Accelerating In-memory Database Functionality with FPGAs13
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS13
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures12
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator12
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs12
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks12
Introduction to the Special Issue on RAW 202412
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains11
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization11
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow11
Cloud Building Block Chip for Creating FPGA and ASIC Clouds9
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units9
Covert-channels in FPGA-enabled SmartSSDs9
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs9
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs8
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs8
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs8
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud8
High-efficiency Compressor Trees for Latest AMD FPGAs7
An FPGA Accelerator for Genome Variant Calling7
VERSATILE: Very Fast Partial Reconfiguration Controller7
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits7
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric7
QUEKUF : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code7
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP7
Introduction to Special Issue on FPGAs in Data Centers7
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns7
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference7
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS7
Introduction to the Special Section on FCCM 20226
xDNN: Inference for Deep Convolutional Neural Networks6
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography6
Strega : An HTTP Server for FPGAs6
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher6
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation6
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs5
CSAIL2019 Crypto-Puzzle Solver Architecture5
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis5
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA5
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition5
Accelerated Phylogenetics on the AMD Versal Adaptive SoC5
Compressing Neural Networks using Learnable 1D Non-Linear Functions5
Data and Computation Reuse in CNNs Using Memristor TCAMs5
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems5
Introduction to the Special Section on FPL 20205
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices5
Introduction to Special Issue on FPGAs in Data Centers, Part II5
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking5
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