IEEE Embedded Systems Letters

Papers
(The median citation count of IEEE Embedded Systems Letters is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)
ArticleCitations
IEEE Embedded Systems Letters Publication Information57
Hyper-Embedded Computing: An Optimized System Architecture for Area-Constrained Applications44
Table of contents32
Online Internal Resistance Computation Based Early Sensing of Thermal Runaway for Smart Fault Handling System (FHS) of Li-ion Batteries26
Privacy-Preserving Anomaly Detection With Homomorphic Encryption for Industrial Control Systems in Critical Infrastructure26
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer22
76.5-Gb/s Viterbi Decoder for Convolutional Codes on GPU22
Editorial19
A New Fast Convergence Speed Q-APL Algorithm for Active Noise Control Applied to Airplane Seats19
Auto Digit Selection for Most Significant Digit First Multiplication18
Fictitious Play Game Theory for Server Deployment Optimization in Edge-Fog Environments18
Design of a Hardware-Efficient Approximate 4-2 Compressor for Multiplications in Image Processing17
Enhancing Perceptual Experience of Video Quality in Drone Communications by Using VPN Bonding16
FloripaSat-2: An Open-Source Platform for CubeSats16
Efficient Nonprofiled Side-Channel Attack Using Multi-Output Classification Neural Network15
Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers14
DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks14
Aging-Aware Parallel Execution14
Controlling a House’s Air-Conditioning Using Nonlinear Model Predictive Control13
Task Sequencing in Frame-Based CPS13
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices12
Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems11
TinyMo: Graph-Level Memory Optimizer for Tiny Machine Learning11
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators11
Configurable Multi-Port Memory Architecture for High-Speed Data Communication10
Editorial10
Development of a Motion Controller for the Electric Wheelchair of Quadriplegic Patients Using Head Movements Recognition10
Impulsive Noise Estimator With Minimization Methods (INEMM) on Software9
Run-Time ROP Attack Detection on Embedded Devices Using Side Channel Power Analysis9
FPonAP: Implementation of Floating Point Operations on Associative Processors9
Co-Designing Perception-Based Autonomous Systems on CPU-GPU Platforms9
Convolutional Neural Network-Based Signal Classification in Real Time8
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes8
ARTS: A Framework for AI-Rooted IoT System Design Automation8
LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites7
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization7
Design of a Low-Cost System for the Measurement of Variables Associated With Air Quality7
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor7
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism7
Respiratory Rate Estimation on Embedded System7
Design of Leading Zero Counters on FPGAs7
Low Consumption Monitoring and Estimation of the State of Charge System for a Hybrid Electric Vehicle6
Wearable Device to Monitor Sheep Behavior6
TinyML-Based Intrusion Detection System for In-Vehicle Network Using Convolutional Neural Network on Embedded Devices6
Using Static Analysis for Enhancing HLS Security6
MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks6
ProMiSE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks6
A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip6
SpiKernel: A Kernel Size Exploration Methodology for Improving Accuracy of the Embedded Spiking Neural Network Systems6
Navigating Time and Energy Trade-Offs in Reactive Heterogeneous Systems5
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack5
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications5
A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor5
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption5
Hardware Trojan Detection Method Against Balanced Controllability Trigger Design5
VANet: A Solution for Ventricular Arrhythmias Detection of IEGM on Embedded Devices5
Optimizing Gaze Estimation With a DLA-Based Calibration Module on NVIDIA Jetson Platforms5
Novel SOH Estimation of Lithium-Ion Batteries for Real-Time Embedded Applications5
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories5
On-Device Personalization for Human Activity Recognition on STM325
GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems5
Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory5
Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures5
EnHDC: Ensemble Learning for Brain-Inspired Hyperdimensional Computing5
Low-Power Synchronization for Multi-IMU WSNs5
IEEE Embedded Systems Letters Publication Information4
Table of contents4
IEEE Embedded Systems Letters Publication Information4
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications4
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs4
Dadu-SV: Accelerate Stereo Vision Processing on NPU4
FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism4
IEEE Embedded Systems Letters Publication Information4
A Control System for Real-Time Driving of LCoS SLM Based on FPGA4
IEEE Embedded Systems Letters Publication Information4
FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images4
LOTUS: A Scalable Framework to Lock Multimodule Designs With One-Time Self-Destructing Key4
Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems4
Empowering Edge Devices With Processing-In-Memory for On-Device Language Inference4
[Blank page]4
IEEE Embedded Systems Letters Publication Information4
Deep Learning-Based Visual Aid for Low Vision4
Methodology for Formal Verification of Hardware Safety Strategies Using SMT4
Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing4
Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis4
Time-Sensitive Networking in Low Latency Cyber-Physical Systems4
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs3
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT3
Lustre, Fast First and Fresh3
Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier3
TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems3
Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks3
LabOSat-01: A Payload for In-Orbit Device Characterization3
Corrections to “FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement”3
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers3
Hardware–Software Co-Optimization of Long-Latency Stochastic Computing3
Toward RISC-V CSR Compliance Testing3
Implementation in FPGA of Alternative Modulation Strategy for Energy Balancing Purposes3
Middleton’s Class A Noise Parameter Estimator3
Predicting Failures in Embedded Systems Using Long Short-Term Inference3
Codesign for Generation of Large Random Sequences on Zynq FPGA3
An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles3
An SoC Design for Future Mobile DNA Detection3
Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU Have Inference Performance Proportional to Respective Priorities3
No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices3
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks3
Ring-DVFS: Reliability-Aware Reinforcement Learning-Based DVFS for Real-Time Embedded Systems3
Hardware and Firmware Design and Implementation of Twin 8-Bit and 32-Bit Microcontroller Boards for Research and Educational Applications3
mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips3
Characterizing CNN Throughput and Energy Under Multithreaded and Multiaccelerator Execution3
Design of an Embedded System for Integrated Underwater Communication and Detection3
Usage-Driven Personalization of Power Management Logic2
Toward an Optimal Countermeasure for Cache Side-Channel Attacks2
Efficient Exact Response Time Analysis for Fixed Priority Scheduling in Lowest Priority First-Based Feasibility Tests2
IEEE Embedded Systems Letters Publication Information2
A Graph Attention Network Approach to Partitioned Scheduling in Real-Time Systems2
Switch-Based High Cardinality Node Detection2
Differentiable Slimming for Memory-Efficient Transformers2
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations2
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory2
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices2
Device-Free Human Motion Detection Using Single Link WiFi Channel Measurements for Building Energy Management2
Point Multiplication Accelerator for Arbitrary Montgomery Curves2
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs2
IEEE Embedded Systems Letters Publication Information2
Three-Stage Power Supply System Model for a Wearable IoT Device for COVID-19 Patients2
Combining Thermal Maps With Inception Neural Networks for Hardware Trojan Detection2
DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs2
Automatic Generation of Reconfiguration Blueprints for IMA Systems Using Reinforcement Learning2
Hardware-Level Secure Coding2
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators2
A Quad-Redundant PLC Architecture for Cyber-Resilient Industrial Control Systems2
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic2
IDRA: An In-Storage Data Reorganization Accelerator for Multidimensional Databases2
Vector Accelerator Unit for Caravel2
Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCs2
Embedded System for Athletes’ Jump Performance Analysis2
Pythia: An Edge-First Agent for State Prediction in High-Dimensional Environments2
A Remote Control System for Emergency Ventilators During SARS-CoV-22
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC2
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators2
Design of Tri-Band Bandpass Filter Using Modified X-Shaped Structure for IoT-Based Wireless Applications2
Dynamic Partial Reconfiguration Profitability for Real-Time Systems2
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition2
Table of Contents1
Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques1
M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs1
Heterogeneous Accelerator Design for Multi-DNN Workloads via Heuristic Optimization1
Implications of Various Preemption Configurations in TSN Networks1
Towards Energy-Accuracy Scalable Multimodal Cognitive Systems1
Reducing ADC Front-End Costs During Training of On-Sensor Printed Multilayer Perceptrons1
Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication1
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing1
Functional Validation of the RISC-V Unlimited Vector Extension1
Optimal Tasks and Heater Scheduling Applied to the Management of CubeSats Battery Lifespan1
Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs1
A New Switching MVC Algorithm for Active Impulsive Noise Control1
An Efficient Edge–Cloud Partitioning of Random Forests for Distributed Sensor Networks1
KOL-4-GEN: Stacked Kolmogorov-Arnold and Generative Adversarial Networks for Malware Binary Classification through Visual Analysis1
Efficient Embedded System for Small Object Detection: A Case Study on Floating Debris in Environmental Monitoring1
Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs1
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures1
XOR-Free Approach for Implementation of Polar Encoder1
HERFA: A Homomorphic Encryption-Based Root-Finding Algorithm1
Power Simulation of a CubeSat: Influence of Orbit, Attitude, and Thermal Control1
Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM1
LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness1
External Timed I/O Semantics Preserving Utilization Optimization for LET-Based Effect Chain1
Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic1
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity1
EvoLP: Self-Evolving Latency Predictor for Model Compression in Real-Time Edge Systems1
Smart Implementation of Industrial Internet of Things Using Embedded Mechatronic System1
Key-Recovery Attack on Enhanced PSLL Techniques1
FPGA-Based Implementation of Single-Cycle High-Throughput LDPC Encoder for 5G New Radio1
Exploring Dynamic Duty Cycling for Energy Efficiency in Coherent DSP ASIC1
Table of Contents1
TENDRA: Targeted Endurance Attack on STT-RAM LLC1
An Explainable and Formal Framework for Hypertension Monitoring Using ECG and PPG1
CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization1
An Embedded Module of Enhanced Turbo Product Code Algorithm1
Evolutionary Recurrent Neural Architecture Search1
FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement1
Enhancing HLS Performance Prediction on FPGAs Through Multimodal Representation Learning1
Reduce Refresh Operations on 3-D TLC nand Flash System via Wordline (WL) Interference1
Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs1
Fault Analysis in Induction Motors Through Signal Acquisition With Hilbert Transform and FPGA1
FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box0
A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security0
Developing Compact Models Using Regression Confidence Forge Knowledge Distillation for IMU‑Based Indoor Positioning System0
Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards0
Hybrid Logic Computing of Binary and Stochastic0
Co-Designing Clusters of Lightweight Manycores and Asymmetric Operating System Kernels0
Table of contents0
Using Intermittent Chaotic Clocks to Secure Cryptographic Chips0
Energy-Efficient Personalized Federated Continual Learning on Edge0
Table of Contents0
A Traceability Localization Method of Acoustic Attack Source for MEMS Gyroscope0
An Embedded Auto-Calibrated Offset Current Compensation Technique for PPG/fNIRS System0
Hardware Deployable Edge-AI Solution for Prescreening of Oral Tongue Lesions Using TinyML on Embedded Devices0
Design and Implementation of an Embedded Edge-Processing Water Quality Monitoring System for Underground Waters0
Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems0
Lightweight Robotic Grasping Model Based on Template Matching and Depth Image0
Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems0
Software Implementation of Fast List Decoder for PAC Codes0
Fast LDPC GPU Decoder for Cloud RAN0
IEEE Embedded Systems Letters Publication Information0
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs0
SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems0
Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays0
LOCoCAT: Low-Overhead Classification of CAN Bus Attack Types0
Flexible Active–Passive and Push–Pull Protocols0
Embedded Systems Education: Experiences With Application-Driven Pedagogy0
RDMA-Based Sampling Port of ARINC-6530
Multistage Multirate Filterbank for FPGA Resource Optimization0
TLP Balancer: Predictive Thread Allocation for Multi-Tenant Inference in Embedded GPUs0
A Template-Based Methodology for Efficient DNNs Inference on FPGA Devices With HW-SW Co-Design0
Cost-Effective Indoor Surveillance System With Multihop Router Network0
Editorial0
An AI-Based Ventilation KPI Using Embedded IoT Devices0
Navigating the Future: A Kalman Filter-Based Global-Local-Global (GLG) Position Estimation for Autonomous Vehicles in GPS Denied Environments0
Table of Contents0
Indoor Collaborative Robot Exploration: A Distributed Market-Based Approach0
CNN Workloads Characterization and Integrated CPU–GPU DVFS Governors on Embedded Systems0
DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash0
An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method0
Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model0
Edge-First Resource Management for Video-Based Applications: A Face Detection Use Case0
Lightweight Surveillance Image Classification Through Hardware-Software Co-Design0
SANGRIA: Stacked Autoencoder Neural Networks With Gradient Boosting for Indoor Localization0
Communication-Efficient Federated Learning With Gradual Layer Freezing0
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module0
Implementation of Polyphase Digital Down Converter Using Optimized LMS Algorithm for WCDMA Application0
Novel Low Memory Footprint DNN Models for Edge Classification of Surgeons’ Postures0
A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures0
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs0
Design of Fault-Tolerant Distributed Cyber–Physical Systems for Smart Environments0
Adversarial Attack Bypass by Stochastic Computing0
Table of Contents0
Software-Defined Watchdog Timers for Cyber-Physical Systems0
Table of Contents0
High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications0
Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators0
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates0
DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference0
Research on Cyclic Queuing and Forwarding With Preemption in Time-Sensitive Networking0
Table of Contents0
Determination of Fiber Content in 3-D Printed Composite Parts Using Image Analysis0
Design, Construction and Measurement of Branchline Coupler0
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style0
IEEE Embedded Systems Letters Publication Information0
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