IEEE Embedded Systems Letters

Papers
(The median citation count of IEEE Embedded Systems Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
Fictitious Play Game Theory for Server Deployment Optimization in Edge–Fog Environments74
Wearable Device to Monitor Sheep Behavior65
EnHDC: Ensemble Learning for Brain-Inspired Hyperdimensional Computing36
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption31
SecCAN: An Extended CAN Controller With Embedded Intrusion Detection26
Design of a Hardware-Efficient Approximate 4-2 Compressor for Multiplications in Image Processing25
IEEE Embedded Systems Letters Publication Information25
A New Fast Convergence Speed q -APL Algorithm for Active Noise Control Applied to Airplane Seats23
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications21
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor21
IEEE Embedded Systems Letters Publication Information20
IEEE Embedded Systems Letters Publication Information20
Implementation in FPGA of Alternative Modulation Strategy for Energy Balancing Purposes18
Table of Contents16
Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis16
DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs15
MetaTinyML: End-to-End Metareasoning Framework for TinyML Platforms15
Design of Tri-Band Bandpass Filter Using Modified X-Shaped Structure for IoT-Based Wireless Applications15
Vector Accelerator Unit for Caravel15
EvoLP: Self-Evolving Latency Predictor for Model Compression in Real-Time Edge Systems14
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity13
Weak PUF-Based Variable Latency Obfuscation Technique for ML-Attack Resilient Arbiter PUFs12
TENDRA: Targeted Endurance Attack on STT-RAM LLC12
GRU-RVCIM: Efficient Implementation of Gated Recurrent Unit in RISC-V - Compute In Memory co-designed for Edge Applications12
CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization12
Efficient Partial Weight Update Techniques for Lightweight On-Device Learning on Tiny Flash-Embedded MCUs11
FPGA-Based RF Signal Generator for Radar Applications11
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection11
Development of a Miniaturized Testing System for Resonant Frequency Difference Detection for Delay Line Surface Acoustic Wave Devices10
A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware10
Editorial10
Software Synthesis From High-Level Specification for Swarm Robotic Applications10
On Automating FPGA Design Build Flow Using GitLab CI10
An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits10
Value-Aware Real-Time Scheduling for Intelligent Transportation Systems10
Toward Precision-Aware Safe Neural-Controlled Cyber–Physical Systems10
On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix10
LION: A Learned Index for On-Device Sensor Data Management9
MQTT-Based Adaptive Estimation Over Distributed Network Using Raspberry Pi Pico W9
Grey Wolf Optimization Algorithm for Embedded Adaptive Filtering Applications9
Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes9
Seeding Algorithm for Bipolar Stochastic Computing for Polynomial Approximations8
ANUBIS: Hybrid FPAA-FPGA Architecture for Entropy-Based True Random Number Generation in Secure UAV Communication8
Cometes: Cross-Device Mapping for Energy and Time-Aware Deployment on Edge Infrastructures8
An Efficient Iterative Beam Search for Human–Robot Collaborative Assembly Line Balancing8
Hardware Deployable Edge-AI Solution for Prescreening of Oral Tongue Lesions Using TinyML on Embedded Devices8
Editorial8
Global Voltage Scaling Across Multiple Cores for Real-Time Workloads8
A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves7
Methodology for CNN Implementation in FPGA-Based Embedded Systems7
CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories7
Toward Dynamism in Distributed Lingua Franca Programs7
JugglePAC: A Pipelined Accumulation Circuit7
Using Intermittent Chaotic Clocks to Secure Cryptographic Chips7
Gradual Channel Estimation Method for TLC NAND Flash Memory7
Exception Coverage on Automotive Processors7
Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes7
Flexible Active–Passive and Push–Pull Protocols7
Instruction-Level Support for Deterministic Dataflow in Real-Time Systems7
An Embedded RISC-V Vector Processor for Energy-Efficient GNSS Signal Processing and Navigation Computation7
Adversarial Attack Bypass by Stochastic Computing7
Impulsive Noise Estimator With Minimization Methods (INEMM) on Software6
Embedded System for the Simultaneous Study of SAHS and Cardiac Arrhythmia6
Editorial6
Optimizing Learned Bloom Filters: How Much Should Be Learned?6
Auto Digit Selection for Most Significant Digit First Multiplication6
TinyMo: Graph-Level Memory Optimizer for Tiny Machine Learning5
Corrections to “FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement”5
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers5
FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism5
Improved Montgomery Modular Multipliers on FPGAs and ASICs5
On-Device Personalization for Human Activity Recognition on STM325
FPGA-Optimized Transformer Network Accelerator with Efficient Softmax and Sparsity-Aware Gating5
DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks5
A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip5
Methodology for Formal Verification of Hardware Safety Strategies Using SMT5
IEEE Embedded Systems Letters Publication Information5
Parallel Optimization of NTT for Kyber Key Encapsulation Mechanism Using GPU-Accelerated Plantard Arithmetic5
ARTS: A Framework for AI-Rooted IoT System Design Automation5
Hardware Trojan Detection Method Against Balanced Controllability Trigger Design5
Privacy-Preserving Anomaly Detection With Homomorphic Encryption for Industrial Control Systems in Critical Infrastructure5
IEEE Embedded Systems Letters Publication Information5
Hardware–Software Co-Optimization of Long-Latency Stochastic Computing5
Time-Sensitive Networking in Low Latency Cyber-Physical Systems5
Differentiable Slimming for Memory-Efficient Transformers5
Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures5
Secure Protocol for Remote Testing Critical Systems Over Public Networks Using Zero-Knowledge Proofs5
Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units5
CSO-TFG: A Configurable Seed-Free On-the-fly Twiddle Factor Generator for NWC-Based NTT/INTT5
Efficient Embedded System for Small Object Detection: A Case Study on Floating Debris in Environmental Monitoring4
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing4
Table of Contents4
QLlama: An FPGA-Based Microscaling Quantization Accelerator for Energy-Efficient Llama2 Inference4
ViTSen: Bridging Vision Transformers and Edge Computing With Advanced In/Near-Sensor Processing4
Data Communication for Low Resources IoT Devices: RS485 Over Electrical Wires4
Common Subexpression-Based Compression and Multiplication of Sparse Constant Matrices4
A Gauge Meter Reader Edge Device Based on Computer Vision and Deep Learning4
Table of Contents4
A Remote Control System for Emergency Ventilators During SARS-CoV-24
Functional Validation of the RISC-V Unlimited Vector Extension4
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT4
No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices4
Table of Contents4
Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM4
MUSIC-Lite: Efficient MUSIC Using Approximate Computing: An OFDM Radar Case Study4
A 340- μ W TinyML Using LUT-Based Reservoir Computing on Low-Cost FPGAs4
Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU4
Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC4
A parallel ring streaming dataflow based convolution array architecture for CNN accelerator4
Implications of Various Preemption Configurations in TSN Networks4
A Sample-Based, Multi-Stage Machine Learning Pipeline for Scalable IoT Threat Detection4
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs4
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs4
Diagnostic Accuracy of Smartphone-Connected Electrophysiological Biosensors for Prediction of Blood Glucose Level in a Type-2 Diabetic Patient Using Machine Learning: A Pilot Study4
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs4
Three-Stage Power Supply System Model for a Wearable IoT Device for COVID-19 Patients4
High Level Synthesis Based Forensic Watermarking of Hardware IPs using IP Vendor’s DNA Signature4
CNN Workloads Characterization and Integrated CPU–GPU DVFS Governors on Embedded Systems3
Renée: New Life for Old Phones3
A Novel Mapping of ECG and PPG to Ensure the Safety of Health Monitoring Applications3
Research on Cyclic Queuing and Forwarding With Preemption in Time-Sensitive Networking3
SENTINEL: Enhancing Trust and Transparency in IoT Networks Through Graph-Based Data Collection and Blockchain3
Navigating the Future: A Kalman Filter-Based Global-Local-Global (GLG) Position Estimation for Autonomous Vehicles in GPS Denied Environments3
Power Efficient Multiplier Design for Error Resilient Edge Applications3
A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security3
An Area and Energy Efficient Serial-Multiplier3
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs3
ArKANe: Accelerating Kolmogorov-Arnold Networks on Reconfigurable Spatial Architectures3
TVI PUF: A Temperature- and Voltage-Independent PUF With High Resistance to Modeling Attacks3
Investigation of Security Vulnerabilities in NVM-Based Persistent TinyML Hardware3
Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model3
RDMA-Based Sampling Port of ARINC-6533
Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks3
Design, Construction, and Measurement of Branchline Coupler3
Hardware-in-the-Loop Simulation of an On-Board Energy-Driven Scheduling Algorithm for CubeSats3
A Low-Cost Embedded System to Support Broadcasting Emergency Messages Through FM Radio Stations3
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools3
EMGAxO: Extending Machine Learning Hardware Generators With Approximate Operators3
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module3
Developing Compact Models Using Regression Confidence Forge Knowledge Distillation for IMU-Based Indoor Positioning System3
A Novel Insight Into the Vulnerability of DDR4 DRAM Cells Across Multiple Hammering Settings3
Table of Contents3
Design of AI-Powered Hybrid Control Algorithm of Robot Vehicle for Enhanced Driving Performance3
Securing RISC-V SoC With Random Clock Self Complementary Countermeasure2
IEEE Embedded Systems Letters Publication Information2
Optimizing Gaze Estimation With a DLA-Based Calibration Module on NVIDIA Jetson Platforms2
Enhanced Prefetching via Dynamic Multi-Step SARSA based Reinforcement Learning2
High-Speed True Random Number Generator With Multiple Entropy Sources: Ring Oscillator Jitter and Random Telegraph Noise2
IEEE Embedded Systems Letters Publication Information2
Low Consumption Monitoring and Estimation of the State of Charge System for a Hybrid Electric Vehicle2
LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites2
Reducing ADC Front-End Costs During Training of On-Sensor Printed Multilayer Perceptrons2
Deterministic Modeling and Simulation of Fault-Tolerant Real-Time Software2
Optimal Tasks and Heater Scheduling Applied to the Management of CubeSats Battery Lifespan2
HLS Trojan Detection Using Machine Learning Technique2
FSMA: Fine-Grained Inter-Layer Scheduling and Mapping Co-Exploration Framework for Chiplet-Based DNN Accelerators2
HLS Watermarking of IP Designs Using Scheduling Driven Key-Based Parallel Switching Framework Integrated With Multimodal Crypto Logic2
Design of Approximate Floating-Point Arithmetic Units Using Hardware-Efficient Rounding Schemes2
Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing2
Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators2
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing2
Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators2
Co-Designing Perception-Based Autonomous Systems on CPU-GPU Platforms2
Middleton’s Class A Noise Parameter Estimator2
Safety-Driven DNN Sizing for Vehicular CPS2
Smart Implementation of Industrial Internet of Things Using Embedded Mechatronic System2
A Quantitative Security Ranking Method of PUF Based on the Rademacher Complexity of PUFs2
A New Switching MVC Algorithm for Active Impulsive Noise Control2
Compressing Runtime Memory Usage via Activation Remapping for Deploying Deep Neural Networks on MCUs2
Padel: Priority-Based Real-Time Scheduling for GPUs2
Deep-Learning-Based Visual Aid for Low Vision2
Optimizing Internal Communication of Compute-in-Memory Based AI Accelerator2
Dadu-SV: Accelerate Stereo Vision Processing on NPU2
Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers2
Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers2
A Robust VMD-PCA Integrated Approach for Accurate Respiration Parameter Estimation From PPG Signals2
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs2
TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems2
Compatibility Analysis and Smooth Transition of Heterogeneous Controllers in Longitudinal Merging Platoons2
HERFA: A Homomorphic Encryption-Based Root-Finding Algorithm2
Low-Power Synchronization for Multi-IMU WSNs2
IEEE Embedded Systems Letters Publication Information2
FPonAP: Implementation of Floating Point Operations on Associative Processors2
An Embedded Module of Enhanced Turbo Product Code Algorithm2
Investigation of the Adversarial Robustness of End-to-End Deep Sensor Fusion Models2
Point Multiplication Accelerator for Arbitrary Montgomery Curves1
Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects1
SoC-Based Implementation of 1-D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML1
Editorial1
Embedded Restricted Boltzmann Machine Approach for Adjustments of Repetitive Physical Activities Using IMU Data1
Table of Contents1
Table of Contents1
SIMMAC: SRAM IMC-Based Multi-bit Multiplication With Analog Carry Computation1
Flipping Bits Like a Pro: Precise Rowhammering on Embedded Devices1
CHISEL: Compression-Aware High-Accuracy Embedded Indoor Localization With Deep Learning1
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack1
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories1
FPGA-Based Real-Time Multi-Class Vehicle Classification Using mmWave Radar1
Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays1
Development of a Motion Controller for the Electric Wheelchair of Quadriplegic Patients Using Head Movements Recognition1
Accelerating LSM-Tree KV Stores via Caching Hot Keys on Hybrid Zoned Storage1
From MLIR to Scheduled CDFG: A Design Flow for Hardware Resource Estimation1
Design and Implementation of Digital Down Converter for WiFi Network1
Embedded System for Quadruped Robot in Mammalian Configuration1
Genelle et al. Revisited: Masking an AES Round With Only Four Secure ANDs1
Communication-Efficient Federated Learning With Gradual Layer Freezing1
Lustre, Fast First, and Fresh1
Heterogeneous Accelerator Design for Multi-DNN Workloads via Heuristic Optimization1
Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems1
Table of Contents1
Energy-Efficient Personalized Federated Continual Learning on Edge1
FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms1
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs1
Container-Based Fail-Operational System Architecture for Software-Defined Vehicles1
Table of Contents1
HDVQ-VAE: Binary Codebook for Hyperdimensional Latent Representations1
Efficient Training and Energy Saving Using Ternary Hardware Acceleration for PCG Classification1
DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference1
Implementation of a Convolutional Neural Network Into an Embedded Device for Polyps Detection1
SpiKernel: A Kernel Size Exploration Methodology for Improving Accuracy of the Embedded Spiking Neural Network Systems1
Software-Defined Watchdog Timers for Cyber-Physical Systems1
A Two-State Energy-Efficient Reliability-Aware Strategy in Embedded Systems1
Optimizing Systolic Array-Based NTT Accelerators1
Characterizing CNN Throughput and Energy Under Multithreaded and Multiaccelerator Execution1
Embedded Systems Education: Experiences With Application-Driven Pedagogy1
An Explainable and Formal Framework for Hypertension Monitoring Using ECG and PPG1
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations1
External Timed I/O Semantics Preserving Utilization Optimization for LET-Based Effect Chain1
Run-Time ROP Attack Detection on Embedded Devices Using Side Channel Power Analysis1
LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency1
Controlling a House’s Air-Conditioning Using Nonlinear Model Predictive Control1
A Flexible Dual-Mode and Efficient RISC-V Coprocessor for On-Node FFT Acceleration in Edge Sensing1
Table of Contents1
IEEE Embedded Systems Letters Publication Information1
Table of Contents1
Real-Time Optical Localization and Tracking of UAV Using Ellipse Detection1
ML-Based Fast and Precise Embedded Rack Detection Software for Docking and Transport of Autonomous Mobile Robots Using 2-D LiDAR1
Lightweight Surveillance Image Classification Through Hardware-Software Co-Design1
Respiratory Rate Estimation on Embedded System1
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer1
Using Static Analysis for Enhancing HLS Security1
Software Implementation of Fast List Decoder for PAC Codes1
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices1
Software-Defined Vehicles: Challenges and Orchestrating Mixed-Criticality Services Using Lingua Franca1
Toward Efficient FPGA Accelerator DSE via Hierarchical and RM-Guided Methods1
LOCoCAT: Low-Overhead Classification of CAN Bus Attack Types1
IEEE Embedded Systems Letters Publication Information1
Location Monitoring System for Sailboats by GPS Using GSM/GPRS Technology1
LLVM-Based Efficient Hybrid Cache and TCM Memory Allocation for Low-Latency1
Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks1
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