IEEE Design & Test

Papers
(The TQCC of IEEE Design & Test is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)
ArticleCitations
ISLPED 2021: The 25th Anniversary!57
BHT-NoC: Blaming Hardware Trojans in NoC Routers52
Top Picks in Hardware and Embedded Security 202243
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions35
IEEE Foundation31
On Backside Probing Techniques and Their Emerging Security Threats30
Special Issue on the 2023 Symposium on Integrated Circuits and Systems Design28
SPOCK: Reverse Packet Traversal for Deadlock Recovery21
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm20
IEEE.tv19
Proceedings of the IEEE18
Front Cover17
IEEE Connects You to a Universe of Information!17
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS17
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method16
ISCA: Intelligent Sense-Compute Adaptive Co-Optimization of Multimodal Machine Learning Kernels for Resilient mHealth Services on Wearables16
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis15
On the Impact of Uncertainties in Silicon-Photonic Neural Networks14
The 2022 International Conference on Computer-Aided Design (ICCAD)14
Report on the 28th Asia and South Pacific Design Automation Conference14
IC Phone Home!14
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond14
edAttack: Hardware Trojan Attack on On-Chip Packet Compression13
Soft and Hard Error-Correction Techniques in STT-MRAM13
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications13
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic13
IEEE Design&Test Publication Information10
IEEE Design & Test Publication Information10
IEEE.tv10
Table of Contents10
Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture9
Energy-Efficient and Error-Resilient Cognitive I/O for 3-D-Integrated Manycore Microprocessors9
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently9
Blank Page9
The Memory Shuffle9
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures8
IEEE Design & Test Publication Information8
Table of Contents8
Get in the Conversation!8
On the Relation Between Reliability and Entropy in Physical Unclonable Functions7
TTTC News7
Remembering Arvind7
Stochastic Computing for Neuromorphic Applications7
Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security7
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration7
CLEAR Cross-Layer Resilience: A Retrospective6
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches6
IEEE Design & Test Publication Information6
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms6
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems6
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems6
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction6
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology6
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators6
IEEE Membership6
Table of Contents6
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery5
IEEE Membership5
Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing5
IEEE Design & Test Publication Information5
Attack of the AI Papers5
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System5
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge5
Robust and Secure Systems5
Front Cover5
Voltage–Resistance-Adaptive MPPT Circuit for Energy Harvesting5
Get in the Conversation!5
Table of Contents5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic5
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The “Chips to Systems Conference”4
Table of Contents4
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O4
Special Issue on Design and Test of Multidie Packages4
Circuits to Systems: Co-Designing Efficient AI Hardware4
Front Cover4
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness4
Guest Editors’ Introduction: SBCCI 20204
A brief history and future perspectives on sizing and layout synthesis of analog/RF integrated circuits4
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning4
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec4
Functional Verification of a RISC-V Vector Accelerator3
Table of Contents3
Long-Wire Leakage: The Threat of Crosstalk3
Testing for Electromigration in Sub-5-nm FinFET Memories3
A BIST Approach to Approximate Co-Testing of Embedded Data Converters3
IEEE Membership3
The 28th IEEE European Test Symposium3
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores3
Table of Contents3
Table of Contents3
Strange Loops in Design and Technology: 59th DAC Keynote Speech3
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction3
TTTC News3
The Future of Design for Test and Silicon Lifecycle Management3
CAFEEN: A Cooperative Approach for Energy-Efficient NoCs With Multiagent Reinforcement Learning3
Seamless Thermal Optimization of Parallel Workloads3
Special Issue on Top Picks in Test and Reliability3
IEEE Design & Test Publication Information3
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking3
IEEE Design & Test Publication Information3
Using STLs for Effective In-Field Test of GPUs3
IEEE Connects You to a Universe of Information!3
ISLPED 2023: International Symposium on Low-Power Electronics and Design3
EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference Designs2
Is There an Answer?2
SBCCI 20222
TTTC News2
Front Cover2
Building an Open-Source DNA Assembler Device2
A Case for PIM Support in General-Purpose Compilers2
3D Ferroelectric NAND In-Storage Processing Architecture for Mass Spectrometry2
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation2
This Stuff Is Great—Am I Right?2
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023)2
SAFER: Safety Assurances for Emergent Behavior2
IEEE Design&Test Is Going Paperless in 2022!2
Special Issue on NOCS 20222
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs2
A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor2
Special Issue on Near-Memory and In-Memory Processing2
IEEE Design&Test Is Going Paperless in 2022!2
IEEE Membership2
Table of Contents2
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications2
GlucoseHD: Predicting Glucose Levels Using Hyperdimensional Computing2
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities2
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata2
Front Cover2
Virtualizing USB Kernel Mode Debug (KMD) Class to Guest OS for Native OS-Like Debug Experience2
Postquantum Cryptography for Internet of Things2
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction2
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network2
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators2
IEEE App2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies2
Guest Editors’ Introduction: SBCCI 20232
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’24)2
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence2
Cloud-Ready Acceleration of Formal Method Techniques for Cyber–Physical Systems2
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