IEEE Design & Test

Papers
(The TQCC of IEEE Design & Test is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-05-01 to 2024-05-01.)
ArticleCitations
A Survey on Energy Management for Mobile and IoT Devices48
Neural Network Inference on Mobile SoCs47
A Survey of Silicon Photonics for Energy-Efficient Manycore Computing38
Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey34
ALIGN: A System for Automating Analog Layout29
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs26
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII25
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security25
GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation23
An Inside Job: Remote Power Analysis Attacks on FPGAs23
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign23
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World21
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators20
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms19
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips17
Secure Interposer-Based Heterogeneous Integration16
Survey on Education for Cyber-Physical Systems16
Discovering CAN Specification Using On-Board Diagnostics13
Spectre Returns! Speculation Attacks Using the Return Stack Buffer13
Real Silicon Using Open-Source EDA12
EM Side Channels in Hardware Security: Attacks and Defenses12
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives11
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks11
Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor11
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads10
Cyber-Physical Systems Security Education Through Hands-on Lab Exercises10
Exact Stochastic Computing Multiplication in Memristive Memory10
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems10
An Open-Source EDA Flow for Asynchronous Logic10
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm10
EdgeAl: A Vision for Deep Learning in the IoT Era10
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology10
Machine Learning for CAD/EDA: The Road Ahead10
OpenTimer v2: A Parallel Incremental Timing Analysis Engine9
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures9
The Role of Competence Networks in the Era of Cyber-Physical Systems — Promoting Knowledge Sharing and Knowledge Exchange9
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN9
A Cautionary Tale About Detecting Malware Using Hardware Performance Counters and Machine Learning9
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots9
Hardware Obfuscation and Logic Locking: A Tutorial Introduction9
Self-Aware Machine Learning for Multimodal Workload Monitoring during Manual Labor on Edge Wearable Sensors9
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor8
Fault: Open-Source EDA’s Missing DFT Toolchain8
On Backside Probing Techniques and Their Emerging Security Threats8
Introducing IoT Subjects to an Existing Curriculum8
Cross-Layer Design of Automotive Systems7
Advances in Design and Test of Monolithic 3-D ICs7
Intelligent Chargers Will Make Mobile Devices Live Longer7
Hardware Virtualization and Task Allocation for Plug-and-Play Automotive Systems7
FaCT-LSTM: Fast and Compact Ternary Architecture for LSTM Recurrent Neural Networks7
A Data-Based Detection Method Against False Data Injection Attacks7
In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing6
Time-to-Digital Converter Compiler for On-Chip Instrumentation6
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels6
Project-Based CPS Education: A Case Study of an Autonomous Driving Student Project6
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection6
A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function6
EDLAB: A Benchmark for Edge Deep Learning Accelerators6
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware6
Design and Test of Crab-Shaped Negative Group Delay Circuit5
Split-Chip Design to Prevent IP Reverse Engineering5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic5
Design Challenges of Intrachiplet and Interchiplet Interconnection5
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures5
Fault-Tolerant Neural Network Accelerators With Selective TMR5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning5
Machine Learning and Algorithms: Let Us Team Up for EDA5
Know Your Channel First, then Calibrate Your mmWave Phased Array5
A Hardware Accelerator for Language-Guided Reinforcement Learning5
Defeating Cache Timing Channels with Hardware Prefetchers5
The AXIOM Project: IoT on Heterogeneous Embedded Platforms5
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance5
Multisensing System for Parkinson’s Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier4
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations4
EDA and Quantum Computing: a symbiotic relationship?4
Autonomous Systems Design: Charting a New Discipline4
Machine Learning in Advanced IC Design: A Methodological Survey4
Automotive Virtual In-sensor Analytics for Securing Vehicular Communication4
Event-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems4
Using STLs for Effective In-Field Test of GPUs4
Hardware Penetration Testing Knocks Your SoCs Off4
The Emerging Majority: Technology and Design for Superconducting Electronics4
Security Vulnerabilities and Countermeasures in MPSoCs4
Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON4
Deadlock-Freedom in Computational Neuroscience Simulators4
Design of Single-Bit Fault-Tolerant Reversible Circuits4
High-Performance Deterministic Stochastic Computing Using Residue Number System3
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge3
SoC Security Evaluation: Reflections on Methodology and Tooling3
Integrating Interobject Scenarios with Intraobject Statecharts for Developing Reactive Systems3
A Programmable Open Architecture Testbed for CPS Education3
Securing CRYSTALS-Kyber in FPGA Using Duplication and Clock Randomization3
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit3
BHT-NoC: Blaming Hardware Trojans in NoC Routers3
Deep Reinforcement Learning for Optimization at Early Design Stages3
Executing Data Integration Effectively and Efficiently Near the Memory3
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift3
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures3
Hunting Security Bugs in SoC Designs: Lessons Learned3
Remote Fault Attacks in Multitenant Cloud FPGAs3
Creating a Foundation for Next-Generation Autonomous Systems3
Coordinated Self-Tuning Thermal Management Controller for Mobile Devices3
Exact Benchmark Circuits for Logic Synthesis3
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.03
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits3
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments3
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies3
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement3
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design3
Runtime Protection of Real-time Critical Control Applications against Known Threats3
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit3
A Conceptual Framework for Stochastic Neuromorphic Computing3
Furthering Moore’s Law Integration Benefits in the Chiplet Era3
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications2
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction2
Hardware-Based Real-Time Workload Forensics2
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware2
Design of ₌׀₌ Shape Stub-Based Negative Group Delay Circuit2
Reverse-Engineering CNN Models Using Side-Channel Attacks2
End-to-End Automated Exploit Generation for Processor Security Validation2
On the Impact of Uncertainties in Silicon-Photonic Neural Networks2
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization2
Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications2
Detecting Pediatric Foot Deformities Using Plantar Pressure Measurements: A Semisupervised Approach2
A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs2
Lifelong Exploratory Navigation: An Architecture for Safer Mobile Robots2
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently2
API-Based Hardware Fault Simulation for DNN Accelerators2
High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction2
Real-time Hardware Implementation of ARM CoreSight Trace Decoder2
Future Engineering Curricula: Balancing Domain Competence with CPS Readiness2
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research2
Self-Healing of Redundant FLASH ADCs2
Vulnerability of Hardware Neural Networks to Dynamic Operation Point Variations2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies2
Cloud-Ready Acceleration of Formal Method Techniques for Cyber–Physical Systems2
An Attachable Battery–Supercapacitor Hybrid for Large Pulsed Load2
Autonomous Systems, Trust, and Guarantees2
Long-Wire Leakage: The Threat of Crosstalk2
Testing of Prebond Through Silicon Vias2
Training Binarized Neural Networks Using Ternary Multipliers2
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators2
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research2
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